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Switched Capacitor Integrator

Discussion in 'Mathematics and Physics' started by MrAl, May 13, 2015.

  1. MrAl

    MrAl Well-Known Member Most Helpful Member

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    Hello there and thanks for your time,

    As most here know, the continuous time integrator in it's simplest form is made with one resistor and one capacitor. The switched capacitor integrator (SCI for short) is made in it's basic form with two capacitors only and one SPDT switch with the switch being typically a CMOS switch controlled by some clock signal. There are more configurations of this integrator (several switches, more capacitors, etc.) but the only one that needs to be considered here is the two capacitor, four SPST CMOS switches controlled with a 50 percent duty cycle clock signal where phase 1 is clock high and phase 2 is inverted clock high, so switches controlled by phase 1 close during the first half cycle and open during the second half cycle, and switches controlled by phase 2 close during the second half cycle and open during the first half cycle. See the attached diagram.

    Now here is the question:

    Supposedly, this formula:
    (0.5* (C2/(C2+C1))* (CONTINUIOUS INTEGRATOR GAIN AT INPUT FREQUENCY)

    can be used to describe the gain of the switched cap filter shown in the diagram. What we would like to do is reach this formula from an analysis of the switched cap filter in the diagram with the four switches. The continuous integrator gain is the gain of a continuous integrator.

    Since i am quite a bit rusty in this area and have no reference books for the switched cap filters anymore i am posing this question in the forum so maybe someone else knows about this already.
     

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  2. wizard

    wizard Member

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    Hi mates...

    Does anyone know the response of the above question please? Especially this part "(0.5* (C2/(C2+C1))" which is put there instead of the input resistor in active low-pass filters (ie Switch-Cap Integrators)

    Thanks.
     
  3. Tony Stewart

    Tony Stewart Well-Known Member Most Helpful Member

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  4. dave

    Dave New Member

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  5. MrAl

    MrAl Well-Known Member Most Helpful Member

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    Hi again,

    Tony:
    That is one of the things we are trying to figure out :)

    Wizard:
    Are you sure you meant to say that the two capacitor expression replaces the resistor in the continuous time integrator?
    One of the things that puzzled me a bit was that expression about the gain of the continuous time integrator:
    "Continuous integrator gain at input frequency"

    But we can only know this gain if we include the resistor or just an expression, for example:
    1/(s*R*C) => 1/(j*w*R*C) => wo/(j*w)

    So i guess what they are saying is that the gain is:
    0.5*C2/(C1+C2)*wo/(j*w)

    but i have to question how we establish what wo is.
    wo must come from the two capacitors also, because that's all we really have to work with.

    Sound right to you or no?
     
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  6. Tony Stewart

    Tony Stewart Well-Known Member Most Helpful Member

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    Still dont know who told you 0.5

    There are two breakpoint frequencies.
    e.g. GBW product and drive current and capacitive load
    Lets assume you need very low Iin and Vio , true for all integrators.
    Then assume you want rail to rail in-out.
    This leads to output ESR in the range of Rs=1K
    Switch rate determine open loop gain from GBW.
    If Switch interval, T1 is slower than RsCfb then Vout =-Cin/Cfb*Vin for initial step.
    Slew rate is limited by both gain and ESR*Cfb
    Ignoring the DC gain from Cap leakage....
    What BW are you using?
    e.g. Good OA http://www.digikey.com/product-detail/en/LMV341MG/NOPB/LMV341MG/NOPBTR-ND/566645
    good film caps can give T2 leakage time constants in minutes.
     
    Last edited: May 14, 2015
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  7. wizard

    wizard Member

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    Hi Al,

    Thank you for your post:).

    If you want to be sure that SC acts as a resistor (Ri) please see these:
    https://classes.yale.edu/04-05/enas627b/lectures/EENG427l04aswcap.pdf
    http://people.rit.edu/lffeee/Selected_Filter_Circuits.pdf (page #21)

    And this one has a table showing the "R" equivalent for different SC typologies:
    http://www.springer.com/cda/content...117904-c1.pdf?SGWID=0-0-45-1485211-p177003162

    Finally please see the section 59.3 of this PDF too:
    http://siliciu.com/files/Carti/carti facultate - selectie pll/VLSI Handbook/CHP59.PDF
     
  8. MrAl

    MrAl Well-Known Member Most Helpful Member

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    Hello again,

    From what i found so far (still working on it) the gain of the switched cap filter is not proportional to C2/(C1+C2), it is proportional to C1/C2.
    The way you can tell is that going from C1=1 and C2=1 to C1=1 and C2=3, if you get a drop in gain of 1/4 of the original then C2/(C1+C2) is true, but if you get a drop in gain of 1/3, then C1/C2 is true. Since i get a drop in gain of 1/3, i have to believe that C1/C2 is the more correct factor. The 0.5 is insignificant in this kind of test because it is the same (or would be the same if it is true) for both sets of capacitor values.
    This is using an op amp that has reasonably normal gain, and that is, maybe 100k or so. Next, i will have to try going through it again with an op amp with lower gain like 1k maybe and see what happens. My last suspicion is that the lower gain causes that C2/(C1+C2) to appear, but that's only a guess at this point so it may turn out to be false also.
    If this last test proves false, then i wont have any choice but to believe that the 'new' formula is either incorrect, wrongly written out, or we dont understand the meaning of the "Continuous integrator gain at the input frequency".

    At least i feel i have made a little progress, for what it is worth :)
     
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  9. Tony Stewart

    Tony Stewart Well-Known Member Most Helpful Member

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    I think someone made an error in their analysis of gain using ω=2πf and used 1/ω=0.5*1/f

    Unless one assumes the switch impedance at 49% is 1/0.49 x ESR of switch.

    The gain, as I indicated is the Cap ratio, just like it us for R ratio using inverting input.

    But I^2R losses and parallel leakage can become factors as extremes and it if ESR of OpAmp limits charge of Cf in the time interval then errors occur, I think.

    The theoretical formula assumes ideal voltage sources charge zero ESR caps with infinite current in zero time.

    This is basically identical to FET input charge amplifiers used for accelerometers except they dont switch.
     
    Last edited: May 15, 2015
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  10. MrAl

    MrAl Well-Known Member Most Helpful Member

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    Hi Tony,

    Well, this is a partly theoretical question anyway, so i dont think we have to consider ESR, but i think we do have to consider finite op amp gain and finite bandwidth. Those two non ideals are accepted for this problem.
    Also not included in this analysis is parasitic capacitance, which is acceptable.
    So we do have to deal with finite gain and bandwidth, but not anything else.
     
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  11. alec_t

    alec_t Well-Known Member Most Helpful Member

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    Perhaps this sim will help inform the discussion:
    SwitchedCapIntegrator.gif
    It is clear from the plot that since C2 = 10 x C1 in this example, it takes 10 steps (10 x the pulse-period) for C2 to charge up to the same voltage that is applied to C1. The output can be deduced as V(out) = -V(in) * (C1/C2) * time/pulse-period.
     
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  12. MrAl

    MrAl Well-Known Member Most Helpful Member

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    Hi,

    Very good Alec. If you like, you can also vary the input frequency (sine wave) and see that the output follows a proportionality to 1/w, and that would pretty much prove that C1/C2 is the more accurate 'gain' factor.
    I am still checking mine which is a non inverting topology, but it looks similar so far.

    If you like, you can also check it using an op amp with somewhat low gain like 1000.
     
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  13. Tony Stewart

    Tony Stewart Well-Known Member Most Helpful Member

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    My simple analysis and assumptions still hold true.

    The effective linear R that controls the LPF slew rate with C ratio steps is thus =T=1/F.
    But we know linear 1st order LPF filters and scopes have a 10-90% slew rate of ~3.3/f-3dB while the linear 1st order ramp has a rise time of 1/(1-e) or 63.2% of the target intercept or asymptote and exponential response exceeds 99% at 5x T or 5/f-3dB. But the latter does not apply here as the response is from a current source Ic=CdV/dt switched at rate, F.

    So what is the Requiv?
    1* 1/FCfb or ?
    1/e * " ? or ?
    0.5 * " or
    3.3/(
    f-3dB Cfb)
    The answer may be found in the actual Fourier Transform or f
    -3dB.
    My math is rusty before 3 cups of coffee....
    I recall that from my S&H mixer designs the F sampling rate mixes signals of same interval to DC at unity mixer gain. The output delta f is the identical waveshape of the signal being sampled, in my case it was a 10MHz sawtooth used for Doppler linear distance motion of accumulated wavelengths counted...as you can tell I have never used a switched Cap LPF but I know they are very powerful with Nth order brick wall LPF's.
     
    Last edited: May 16, 2015
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  14. MrAl

    MrAl Well-Known Member Most Helpful Member

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    Hello again,

    Well in any case, here is a complete simulation with comparisons to the two ways of calculating the gain: either C1/C2 or the 'new' C2/(C1+C2).
    This shows that the calculation using C1/C2 comes much closer to the graphically measured data than C2/(C1+C2). Therefore i can only believe that either that new formula is wrong, or it is being applied to the wrong circuit, or there is something else missing from the formula that is not apparent by simple inspection.

    Here is a picture of the simulations (see attachment).
    First note that the general simulated output is actually the non inverted time integration of the input voltage as expected. We can tell this because of the phase shift.
    Note that three values of C2 were used: 1uf, 3uf, and 5uf, while C1 was held constant at 1uf for all three simulations.
    Also note that the simulation voltage outputs are all shown in red, with amplitudes decreasing as C2 goes up in value.
    Also note that the results predicted using the calculation C2/(C1+C2) are shown in green for C2=3uf and black for C2=5uf, and the highest amplitude red is also the predicted output for C2=1uf but only after assuming that the formula is correct to begin with (this is necessary for a direct comparison like this, and also see the "LATER NOTE" note below for more info about this).

    Since the predicted output using C2/(C1+C2) goes down as C2 changes from 1uf to 3uf, but then goes up as C2 changes from 3uf to 5uf, there must be something wrong with that formula or it's application.

    Check out the attachment and feel free to strongly critique any issues you might think of and ask any question no matter how mundane it might seem.

    LATER NOTE:
    Note that the more exact calculation for C2/(C1+C2) given the reference output of 2.5 volts peak (rounded to 2.5 from 2.53 for convenience) is as follows...
    The input is 0.05v peak, and the output is 2.5v peak. The overall gain must be 50, with part of that being because of the cap combination. So we have to start:
    2.5=C2/(C1+C2)*K*0.05
    so here we see that:
    K*C2/(C1+C2)=50
    and that is when C1=1 and C2=1 (in uf) so we have:
    1/(1+1)*K=50
    so we have:
    K=100
    and that is constant.
    So with C1=1 and C2=1 we have:
    1/2*K=50
    and so the output is:
    50*0.05=2.5 volts peak (the highest red output shown in the attachment).

    For the test, next we have to increase C2 to 3uf, so we end up with:
    3/(1+3)*K=3/4*100=75
    and since we have the same input we have as output:
    Vout=75*0.05=3.75 volts peak.

    Now already we see that we went from an output of 2.5v to an output of 3.75v, so something looks wrong already.
    Continuing with the test, we increase C2 to 5uf, and we get a gain of:
    5/(1+5)*K=5/6*100=83.33
    and so an output of:
    0.05*83.3=4.17 volts peak.

    So the output went from 2.5v to 3.75v to 4.17v, which does not follow logically. It should be going down with C2 regardless what formula we use.
    Note the input frequency is constant so any "Continuous integrator gain" should be constant too.

    See the second attachment for these more exact waveforms.
     

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    Last edited: May 18, 2015
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  15. MrAl

    MrAl Well-Known Member Most Helpful Member

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    Hello again,

    Another possibility is that the Continuous integrator gain should be adjusted when C2 is adjusted. This means that we might instead have an overall gain as:
    G=K*C2/(C1+C2)*1/(w*C2)

    This added factor would change the whole thing to:
    G=K/(w*(C1+C2))

    which would make a little more sense anyway, except the ratios still dont work.

    For C1=1uf and C2=1uf if we get 1.5v out, then with c2=3uf using C1/C2 we would get 0.5v out (observed) but using 1/(C1+C2) we would get only 0.375v out, so it still looks like C1/C2 is the better choice.
     
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  16. Tony Stewart

    Tony Stewart Well-Known Member Most Helpful Member

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    Be sure that you are not current limiting (Iop) your design with ESR of OpAmp with capacitive load Zc.

    - using Zc=1/2πfC and for a sinusoidal f, Iop=Vp/Zc For Vp= peak sine output w.r.t. Vin(ref) usually 0V.

    Thus Iop=Vp*2πfC @500Hz , 5μF , Iop=Vp*63.7 mA


    Does this exceed your device current limit?

    Thats why it does not follow Av=kf C2/C1 !!
     
    Last edited: May 19, 2015
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  17. MrAl

    MrAl Well-Known Member Most Helpful Member

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    Hi,

    I am not sure what you are saying. It appears to follow K*C1/C2. Note i leave out frequency because we can make that a constant for the tests. If we cant get it to work with a constant frequency then we sure as heck cant get it to work with a variable frequency.
     
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  18. Tony Stewart

    Tony Stewart Well-Known Member Most Helpful Member

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    Then reduce your Cap values by at least 1 or 2 orders of magnitude.

    And as usual for integrators for low leakage, use film caps, but for accuracy use NP0.
     
    Last edited: May 19, 2015
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  19. MrAl

    MrAl Well-Known Member Most Helpful Member

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    Hello,

    Tony, this is a theoretical example where we dont have any leakage for example, and we can make the cap values anything including 1e-12 pf (that is a 1 pico pico farad cap, 1e-24 Farad) and still get it to work perfectly.
     
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  20. Tony Stewart

    Tony Stewart Well-Known Member Most Helpful Member

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    Since you didnt report any changes with my suggestion, Istill dont understand the issue now.
     
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  21. alec_t

    alec_t Well-Known Member Most Helpful Member

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    Can you post a link to the original text for this prof's formula? That should identify the relevant circuit configuration it allegedly applies to. I still think the new 'C1+C2' bit can only come from the caps being paralleled rather than sampled as per your circuit.
     
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