Hello there and thanks for your time,
As most here know, the continuous time integrator in it's simplest form is made with one resistor and one capacitor. The switched capacitor integrator (SCI for short) is made in it's basic form with two capacitors only and one SPDT switch with the switch being typically a CMOS switch controlled by some clock signal. There are more configurations of this integrator (several switches, more capacitors, etc.) but the only one that needs to be considered here is the two capacitor, four SPST CMOS switches controlled with a 50 percent duty cycle clock signal where phase 1 is clock high and phase 2 is inverted clock high, so switches controlled by phase 1 close during the first half cycle and open during the second half cycle, and switches controlled by phase 2 close during the second half cycle and open during the first half cycle. See the attached diagram.
Now here is the question:
Supposedly, this formula:
(0.5* (C2/(C2+C1))* (CONTINUIOUS INTEGRATOR GAIN AT INPUT FREQUENCY)
can be used to describe the gain of the switched cap filter shown in the diagram. What we would like to do is reach this formula from an analysis of the switched cap filter in the diagram with the four switches. The continuous integrator gain is the gain of a continuous integrator.
Since i am quite a bit rusty in this area and have no reference books for the switched cap filters anymore i am posing this question in the forum so maybe someone else knows about this already.
As most here know, the continuous time integrator in it's simplest form is made with one resistor and one capacitor. The switched capacitor integrator (SCI for short) is made in it's basic form with two capacitors only and one SPDT switch with the switch being typically a CMOS switch controlled by some clock signal. There are more configurations of this integrator (several switches, more capacitors, etc.) but the only one that needs to be considered here is the two capacitor, four SPST CMOS switches controlled with a 50 percent duty cycle clock signal where phase 1 is clock high and phase 2 is inverted clock high, so switches controlled by phase 1 close during the first half cycle and open during the second half cycle, and switches controlled by phase 2 close during the second half cycle and open during the first half cycle. See the attached diagram.
Now here is the question:
Supposedly, this formula:
(0.5* (C2/(C2+C1))* (CONTINUIOUS INTEGRATOR GAIN AT INPUT FREQUENCY)
can be used to describe the gain of the switched cap filter shown in the diagram. What we would like to do is reach this formula from an analysis of the switched cap filter in the diagram with the four switches. The continuous integrator gain is the gain of a continuous integrator.
Since i am quite a bit rusty in this area and have no reference books for the switched cap filters anymore i am posing this question in the forum so maybe someone else knows about this already.