Module osc1322
Config
FOSC = IRC, ' internal RC osc
PLLEN = OFF, ' PLL is under software control
PCLKEN = OFF, ' Primary clock drive disabled (using internal)
FCMEN = OFF, ' Fail-Safe Clock Monitor disabled
IESO = OFF, ' Oscillator Switchover mode disabled
PWRTEN = ON, ' PWRT enabled
BOREN = OFF, ' Brown-out Reset disabled in hardware and software
BORV = 22, ' VBOR set to 2.2 V nominal
WDTEN = OFF, ' WDT is controlled by SWDTEN bit of the WDTCON register
WDTPS = 128, ' 1:128
MCLRE = ON, ' RA3 input pin disabled; MCLR enabled
HFOFST = OFF, ' The system clock is held off until the HFINTOSC is stable.
STVREN = ON, 'Stack full/underflow will cause Reset
LVP = OFF, ' Single-Supply ICSP disabled
BBSIZ = OFF, ' 1KW boot block size
XINST = OFF, ' Instruction set extension and Indexed Addressing mode disabled
DEBUG = OFF
OSCCON = %01100010 // IRCF=8MHz, SCS1=1 (int osc)
OSCCON2 = 0
OSCTUNE = %10000000 // INTSRC=1, PLLEN=0, TUN=0
// set all pins digital
ANSEL = $00
ANSELH = $00
CM1CON0 = 0
CM2CON0 = 0
VREFCON1 = $00