N-ch MOSFET drain-source voltage loss

[earckens]

Mosfet Q5 (located in D3 in attached schematic) is driven by 6V on the gate, drain voltage is 12V, yet source only gives 8V, load just a few mA.

It's twin Q3 behaves better: source voltage is 11V with gate at 8V.

What is the reason?
Should I decrease R34 (D6) from 410k to a lower value (without compromising the C11 R29 time constant (C5))?

Mosfet datasheet attached.

 

[dknguyen]

Q5 is the twin? You said Q3 was the twin of itself.

 

[earckens]

Q5 is the twin? You said Q3 was the twin of itself.

Sorry, yes should be Q5 that is twin; I just edited my first post to correct this.

 

[dknguyen]

And instead of R34, I think you mean R19.

What are the details of D3 and D4? Are they identical?

Is D3 actually not lighting up? Because you are using NMOSs on the high-side with the LED and resistor acting as negative feedback so you would not expect either Q3 or Q4 to fully turn on and have 12V appear at their source pins.

If they are identical LEDs, that's pretty weird if it's different since the two circuits look identical to me. Try shorting across the D3 and D4 and measuring the drain voltage of Q3 and Q5 to see if they are the same. They should be.

 

[earckens]

And instead of R34, I think you mean R19.

What are the details of D3 and D4? Are they identical?

Is D3 actually not lighting up? Because you are using NMOSs on the high-side with the LED and resistor acting as negative feedback so you would not expect either Q3 or Q4 to fully turn on and have 12V appear at their source pins.

If they are identical LEDs, that's pretty weird if it's different since the two circuits look identical to me. Are you sure it's not a bad or mistaken component somewhere? Try shorting across the D3 and D4 and measuring the drain voltage of Q3 and Q5 to see if they are the same.

OMG , I am truly sorry for these mistakes dknguyen!!

The culprit is Q3 that behaves badly, its twin Q5 is ok.

I re-edited my first post again , thanks for your patience!

D3 is a red 0603 SMD led, D4 is yellow.

Both D3 and D4 do light up when the mosfet is conducting. Voltage across is 2V.

Is it not-done to have n-ch on the high side?

 

[earckens]

(.....)

If they are identical LEDs, that's pretty weird if it's different since the two circuits look identical to me. Are you sure it's not a bad or mistaken component somewhere? Try shorting across the D3 and D4 and measuring the drain voltage of Q3 and Q5 to see if they are the same.

Hi dknguyen, ok, I try that and come back here with the results.

Should I change the n-channel set-up to low-side (same for Q1 in A1 and Q13 in C3)?

 

[dknguyen]

Hi dknguyen, ok, I try that and come back here with the results.

Should I change the n-channel set-up to low-side (same for Q1 in A1 and Q13 in C3)?

No, leave it alone. See below.

Is it not-done to have n-ch on the high side?

You can actually do it both ways. Having the N-channel on the high-side allows you to get away with no LED current limiting resistors. The negative feedback allows the extra voltage to dissipate across the NMOS itself. This means the NMOS does not fully turn on.

Putting the N-channel on the low-side has the NMOS fully turn on, but then you need current limiting resistors for the LED.

In your case, since you actually need the current limiting resistors because they are being used as a voltage divider, then there might be a veryyyyy slightly benefit in having the NMOS on the low-side but probably nothing you would notice. The only real benefit I can see is that the circuit with the resistive divider in there is easier to analyze compared to the NMOS on the high-side.

I think the reason is probably the two LEDs are different forward voltages so that's why you get different voltages on the source pin. To confirm, do the test I mentioned and short both LEDs and measure the FET source voltages. See if they are the same.

If the shorted LED test has the same voltage on the source pins of the NMOS, then there is no problem with your circuit. The problem is just your understanding of the circuit which is is causing you to have the wrong expectations.

 

[MikeMl]

earckens

You seem to be confused about how a source-follower works. Note that V(s) follows V(g), but there is an offset determined by Vth (threshold Voltage) of the NFET. Note that V(g) has to exceed Vth before the source follows. Note that the source cannot follow any higher than V(d)=12V.

Two NFETs of the same part number can have radically different Vth.

 

[earckens]

No, leave it alone. See below.

You can actually do it both ways. Having the N-channel on the high-side allows you to get away with no LED current limiting resistors. The negative feedback allows the extra voltage to dissipate across the NMOS itself. This means the NMOS does not fully turn on.

Putting the N-channel on the low-side has the NMOS fully turn on, but then you need current limiting resistors for the LED.

In your case, since you actually need the current limiting resistors because they are being used as a voltage divider, then there might be a veryyyyy slightly benefit in having the NMOS on the low-side but probably nothing you would notice. The only real benefit I can see is that the circuit with the resistive divider in there is easier to analyze compared to the NMOS on the high-side.

The voltage divider result is quite critical, there only is a slim tolerance and I need to be sure that the resulting voltage is within these limits (2.6V to 3.4V): would it not be safer to use low side n-channel because then I will be sure there is no voltage drop across the mosfet?

I think the reason is probably the two LEDs are different forward voltages so that's why you get different voltages on the source pin. To confirm, do the test I mentioned and short both LEDs and measure the FET source voltages. See if they are the same.

Drain always at 11.1V
Q5: LED=on G=6.4V, S=8.0V LED=shorted G=6.4V, S=8.0V
Q3: LED=on G=8.0V, S=8.0V LED=shorted G=8.0V, S=10.5V
Why would the gate voltage of Q5 be higher?

If the shorted LED test has the same voltage on the source pins of the NMOS, then there is no problem with your circuit. The problem is just your understanding of the circuit which is is causing you to have the wrong expectations.

Right; thanks a lot for your time and explanations!

 

[dknguyen]

The voltage divider result is quite critical, there only is a slim tolerance and I need to be sure that the resulting voltage is within these limits (2.6V to 3.4V): would it not be safer to use low side n-channel because then I will be sure there is no voltage drop across the mosfet?

It doesn't really matter because you can always compensate by adjusting the divider ratio. If you've already got it adjusted then no need to change it. As far as I can tell, it's just a matter of ease of analysis rather than actual functionality.

Drain always at 11.1V
Q5: LED=on G=6.4V, S=8.0V LED=shorted G=6.4V, S=8.0V
Q3: LED=on G=8.0V, S=8.0V LED=shorted G=8.0V, S=10.5V
Why would the gate voltage of Q5 be higher?

That must mean there's some difference in your circuit upstream which I don't have the wherewithal to search for right now. The circuits looked identical to me when I skimmed it earlier though. Odd.

 

[earckens]

It doesn't really matter because you can always compensate by adjusting the divider ratio. If you've already got it adjusted then no need to change it. As far as I can tell, it's just a matter of ease of analysis rather than actual functionality.

Hi dknguyen, if you had designed it, would you choose high-side for the NMOS?
I ask because now it seems more logical to use high-side, yet when I read your comment above here you recommend both can be used as long as the consequences as you and MikeMI above have described are considered.

That must mean there's some difference in your circuit upstream which I don't have the wherewithal to search for right now. The circuits looked identical to me when I skimmed it earlier though. Odd.

I checked all components involved, no difference to be seen. For this reason I would start to think that choosing the high-side versus this design has the advantage of making sure the mosfets behave like digital switches, no intermediate state and always 0V across when conducting. Or do I make the wrong assumption?

 

[dknguyen]

Hi dknguyen, if you had designed it, would you choose high-side for the NMOS?
I ask because now it seems more logical to use high-side, yet when I read your comment above here you recommend both can be used as long as the consequences as you and MikeMI above have described are considered.

For your very specific case with the resistive divider I would have gone low-side just because it's more straightforward for me to analyze. If I was just lighting an LED, I would have gone high side.

I checked all components involved, no difference to be seen. For this reason I would start to think that choosing the high-side versus this design has the advantage of making sure the mosfets behave like digital switches, no intermediate state and always 0V across when conducting. Or do I make the wrong assumption?

The low-side is the one where it would always behave like a digital switch.

 

[MikeMl]

It looks like the gate drive to Q3 and/or Q5 is either zeroV or 12V (confirm this?).

If so, you are right at the Absolute Max rating for Vgs of the AO3400A if you ground the source of the NFet (common source mode) and put the LED load in the drain lead.

Since the gate is swinging from zero V to 12V, I see nothing wrong with connecting the NFet as a source -follower (common-drain).

 

[earckens]

It looks like the gate drive to Q3 and/or Q5 is either zeroV or 12V (confirm this?).

Indeed.

If so, you are right at the Absolute Max rating for Vgs of the AO3400A if you ground the source of the NFet (common source mode) and put the LED load in the drain lead.

Since the gate is swinging from zero V to 12V, I see nothing wrong with connecting the NFet as a source -follower (common-drain).

You mean, as it is done now, drain to supply and source to load?

 

[earckens]

I may yet have a P-channel available with G-S threshold voltage of 1.5V to 3.5V which I plan to use to switch power on and off to the whole sensor H-bridge section (12V 200mA). But the microcontroller needs to switch its gate, with 3V: would that work?

 

[dknguyen]

I may yet have a P-channel available with G-S threshold voltage of 1.5V to 3.5V which I plan to use to switch power on and off to the whole sensor H-bridge section (12V 200mA). But the microcontroller needs to switch its gate, with 3V: would that work?

When using a MOSFET as a switch, pay less attention to the gate threshold voltage and more attention to the voltage at which the on-resistance is measured at.

 

[earckens]

When using a MOSFET as a switch, pay less attention to the gate threshold voltage and more attention to the voltage at which the on-resistance is measured at.

Why? If I use a mosfet to be switched by this 3V microcontroller should the gate-source threshold voltage impact its functioning?
For example a P-channel mosfet drain connected to the supply (12V), source to load and gate driven by a 3V digital controller output..

 

[dknguyen]

Why? If I use a mosfet to be switched by this 3V microcontroller should the gate-source threshold voltage impact its functioning?
For example a P-channel mosfet drain connected to the supply (12V), source to load and gate driven by a 3V digital controller output..

The gate-threshold voltage is just that: the threshold. It's when the MOSFET just STARTS to conduct anything at all. This is not the same as the MOSFET being fully on and fully conducting.

 

[MikeMl]

...

You mean, as it is done now, drain to supply and source to load?

.

No, as it is done now, V(g) is not more than Vth above V(s), or Vgs =Vth, which is clearly within the Absolute Max Rating.

If you use a NFET and put the loads in its drain, then since Vs is ground, Vg max = 12V, which is right at the max limit.

If you use a PFET (source connected to +12V) and put the load between its drain and ground, then the gate swing must be constrained to be between 12V (PFET turned off), and ~2V (PFET turned on hard, Vgs = -10V max). This would keep the Vgs of the PFET within its Absolute Max Rating limits.

 

[earckens]

The gate-threshold voltage is just that: the threshold. It's when the MOSFET just STARTS to conduct anything at all. This is not the same as the MOSFET being fully on and fully conducting.

Ah ok; what would you recommend as characteristics for a p-channel mosfet with load connected to its source, with a 12V supply to be switched and a lod of about 200mA. And the gate driven by the 3V digital output of a microcontroller?