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Mosfets drain (n type the tab on to-220 mosfets)

MrDEB

Well-Known Member
I want to attach all 8 tabs to the circuit board as heat sink but can I attach all 8 on together on the circuit board?
 
Here is a revised footprint that does work. No DRC errors or other issues.

to-220 revised 1.jpg


to-220 revised 2.jpg
 

Attachments

  • PCBLIB_PCBLIB_TO-220 HORIZONTAL_2024-04-12 + HEATSINK-TEST6_2024-04-18 (2).zip
    2.1 KB · Views: 71
Here's some guidance from the EasyEDA forum for including multiple copper areas in a footprint.


How to avoid DRC errors when connecting to PCB Footprints (a.k.a. PCB Libs)

andyfierman 4 years ago

The basic problem when constructing PCB Footprints (a.k.a. PCB Libs) is that anything made of copper in a PCB Footprint that is not a pad will generate a DRC error with surrounding or connecting copper on the PCB.
Here are some rules for making a PCB Footprint that will avoid generating these DRC errors:
  1. Everything made of copper - including any connections between pads and mounting holes with copper around and/or through plated - must be made using Top, Bottom or Multi Layer pads, whether round, oval, rectangular or polygons and editing the points;
  2. Holes without copper should be made using the Hole tool or Solid region set as Board Cutout;
  3. All pads should be numbered but different pads can have the same number. For example, for a TO-220 packaged power transistor which has 3 pins on the symbol (CBE or DGS) but has 4 electrical connections to the pins and the tab that need to be mapped onto 4 pads so two of the pads can have the same number assigned to them;
  4. All pads that are connected together by copper (see (1) above) must have the same number;
  5. Do not try to use vias in a PCB footprint. Use a multilayer pad set to the same dimensions as a via (for more on this, see: https://easyeda.com/forum/topic/How...CB-footprint-a34cf68d58414138898a56de60abd8c1);
  6. Because they cannot be assigned pad numbers, the following elements of Tracks, Arcs, or Solid Regions should only be used to create copper elements in PCB Footprints if they are selected after placement, right-clicked on and then Converted to Pads;
  7. Because they cannot be assigned pad numbers and cannot be converted to pads, the following elements of Rectangles, Circles, Text or imported images should not be used in the construction of copper elements in a PCB Footprint. If a PCB Footprint containing such elements is then placed on a PCB, wherever a track or copper area crosses or passes too close to any of these elements, it will generate DRC errors. The only exception to this is when such elements are placed within and completely surrounded by a pad so that they cannot be connected to. An example of this is shown in: https://easyeda.com/andyfierman/avoiding-drc-errors-in-footprints;
  8. Do not assign Nets to any part of a PCB Footprint: they will generate DRC errors because there is no guarantee that a net with the same name as that assigned to a pad in the Footprint, will be connected to that pad by everyone who uses that Footprint. For example, what one user may call GND in a PCB Footprint, may be connected by another user, to a net in the PCB called GRND, Earth, 0V or something entirely different like VSS;
  9. As described in (3) above, the Schematic Symbol for a device may have fewer pins than the number of electrical connections to the physical package. For example, discrete MOSFETs usually have only a gate, source and drain connection but many are packaged so that although there is a Gate is connected to a single pad, the Source may be connected to 3 pads, which are all directly shorted together on or within the package and the Drain to 4 pads. To avoid over complicating the Schematic Symbol - and therefore cluttering up the Schematic - this is easily and most effectively handled by mapping each pin on the Schematic Symbol onto one or more pads, assigned the same number, on the PCB Footprint;
  10. A PCB Footprint must not have fewer pads than the number of pins on the device that is to be placed on it. Do not omit pads for unconnected or NC pins on the device: they are often required for mechanical or thermal stability. This must include things like, for example, ground and shield pins on USB and Ethernet connectors.
Below is a topic that illustrates some of these issues and their solutions according to these rules:
https://easyeda.com/forum/topic/Drc-errors-with-library-component-f42b0deca29a47df944623bbeff22184
 
Here is a revised footprint that does work. No DRC errors or other issues.

View attachment 145392

View attachment 145393
If the via stitching is to improve heat transfer from the top to the bottom layer, it would be better for them to be close to the heat source.

As shown above, the thermal path from the device to the center of the bottom pad is relatively long. Putting the vias under the device will make the bottom area much more efficient.

There will be a lot of heat conducted by the bolt, but if you're adding vias, they should be placed where they will do the most good.
 
There will be a lot of heat conducted by the bolt, but if you're adding vias, they should be placed where they will do the most good.

Good point, but I'm reluctant to put vias under the tab so as to provide the smoothest surface under the tab.
 
here is my circuit board free of any DRC errors. On the heat sink pads I found just putting a top layer and bottom layer seems to work. Using multi-layer seems to go south so I am just using top and bottom layers. Maybe the wrong approach. This is an EASYeda file
 

Attachments

  • PCB_final-marg-sign_2024-04-19.zip
    340.4 KB · Views: 64
So you didn't even try my revised footprint? That I spent a couple hours working on on your behalf?
Guess I know when to cut my losses.
 
Not that I give a rat's a$$, but I don't think your board is going to work very well. I don't think I'd run three traces between the pads on 1206 resistors (and there are many places where clearance is really tight where's there's no need) but that's not the fatal flaw.......

Debs latest folly.png
 
I tried your new footprint but the bottom layer didn't have any pad. I ran into this when using multi-layers.
Will recheck my layout as per post 127.
 
Works fine for me, using the footprint in post #121. The pictures are YOUR board, with my footprint.

You apparently don't see the problem in post #127. That's your board. What happens when you bend the MOSFETs over?


Debs latest folly 2.png


Debs latest folly 3.png
 
So let me get this straight.

  • In post 109, I made a custom footprint for you that I thought would work.
  • In post 114, you tried it and it did not work properly. My apologies.
  • In post 121, I posted a revised footprint that I had tested in an actual circuit, and posted pictures documenting it did work. This took a couple hours to find the proper method to build a multilayer footprint.
  • In post 128, you said my footprint didn't work but this wasn't the REVISED FOOTPRINT from post 121; it was the original footprint from post 109. Despite the warnings I had posted between post 109 – 121 not to use it.
  • In post 131, you finally say you downloaded the new footprint from post 121. After you had claimed that it didn't work in post 128.[/B]

Did I miss anything? You don't have to take my advice or suggestions (and Lord knows why I continue to try) but don't claim something didn't work when you didn't even try it. It's a wonder anybody attempts to help you.
 
You've probably figured this out, but just in case.....

Draw the schematic using the correct part number MOSFET. Then select each MOSFET, and in the properties menu on the right, click the footprint box to update the footprint. Search for the TO-220 footprint in the workspace library.

You can do this one at a time, several at a time by pressing [CNTL] while selecting multiple or, if you're starting with a fresh schematic, changing the first MOSFET, then copying it as many times as needed.

If you're using the existing schematic, no need to do anything but update each footprint in the schematic.
 
Not that I give a rat's a$$, but I don't think your board is going to work very well. I don't think I'd run three traces between the pads on 1206 resistors (and there are many places where clearance is really tight where's there's no need) but that's not the fatal flaw.......

View attachment 145410
Just making a guess as im only just learning this stuff. Is the problem you mention, right hand side will have plastic on the foot print doodha, and the other side has what looks metal to metal? so bending them on right (if Ive read this thread correctly) going to be no point bending plastic onto metal for cooling?? Or am I missing something obv ios?
 
Exactly right!
 
I corrected the mosfet layouts and pasted the footprint from post#121.
Everythig going well until I ran the DRC. The standard edition of easyeda has numerous issues like freezing up.
Downloaded the pro version and going to try it out. Maybe it will work?
 
Sorry you're having issues. I have experienced very few problems with the standard version of EasyEDA. I don't use the pro version because it doesn't have some of the features I use in the standard version.

You should ask for help in the EasyEDA forum if you're having problems with EasyEDA.
 
Are the errors indicated legitimate?
 

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