N-ch MOSFET drain-source voltage loss

[dknguyen]

Ah ok; what would you recommend as characteristics for a p-channel mosfet with load connected to its source, with a 12V supply to be switched and a lod of about 200mA. And the gate driven by the 3V digital output of a microcontroller?

A PMOS with the load connected to its source would be on the low-side (opposite of an NMOS). Are you sure you don't mean a PMOS with it's loaded connected to it's drain? There is little point putting a PMOS on the low-side as a supply switch because you could just use an NMOS which is cheaper, more efficient, and easier to control. The whole point of a PMOS is so that you can put it on the high-side to not disturb the ground path.

But the problem in this configuration is that the PMOS on the high-side will never be able to turn off if the gate is driven directly because the MCU can pull the gate towards ground to turn the PMOS off, but it can never output a high enough voltage (12V) to turn the PMOS off. In this instance, the voltage is limited by the PMOS's gate voltage (which is always less than the maximum source-drain voltage) since the gate voltage will see the full supply voltage when the gate is pulled to ground to turn the PMOS on.

So using a PMOS on the high-side requires a max gate voltage that is at least as high as the supply voltage. The max source-drain voltage doesn't need to be looked at in this case since it is always higher.

 

[MikeMl]

Here is a prototype PFET high-side driver. You have to understand this before you worry about driving it from a 3.3V micro...

Note that the gate drive is referenced to the +12V line; not gnd. If V(g) = 12V, the PFET is off (Vgs=0V).

As V(g) decreases from 12V toward ~11V (Vgs=-1V), the PFET begins turning on, pulling its drain V(d) toward +12V in-spite of the 6Ω load.

By the time V(g) reaches ~10V (Vgs=-2V), the PFET is turned on about as hard as it needs to be to deliver 2A to the 6Ω load resistor. Note the power dissipation in the PFET (the violet trace) as Vgs moves from 0V to -4V, which is the X-axis of the plot.

As the Vgs drive is increased (decreased?) from -1V to -4V, the PFET turns on better, reducing its Ron, and thereby reducing the power lost in the PFET.

In a subsequent post, I will show how to drive this from a micro pin that swings from 0V to 3.3V, but I want you to understand this post first.

 

[earckens]

A PMOS with the load connected to its source would be on the low-side (opposite of an NMOS). Are you sure you don't mean a PMOS with it's loaded connected to it's drain? There is little point putting a PMOS on the low-side as a supply switch because you could just use an NMOS which is cheaper, more efficient, and easier to control. The whole point of a PMOS is so that you can put it on the high-side to not disturb the ground path.

But the problem in this configuration is that the PMOS on the high-side will never be able to turn off if the gate is driven directly because the MCU can pull the gate towards ground to turn the PMOS off, but it can never output a high enough voltage (12V) to turn the PMOS off. In this instance, the voltage is limited by the PMOS's gate voltage (which is always less than the maximum source-drain voltage) since the gate voltage will see the full supply voltage when the gate is pulled to ground to turn the PMOS on.

No, I am not sure at all: I just want to switch the 12V supply to the sensors on and of using a mosfet and a 3V microcontroller output. I did not realise your comment in the last paragraph.
So, a solution to switch 12V to the load represented by the sensors, driven by a 3V gate voltage would be very helpful.

 

[earckens]

Here is a prototype PFET high-side driver. You have to understand this before you worry about driving it from a 3.3V micro...


View attachment 112585

Note that the gate drive is referenced to the +12V line; not gnd. If V(g) = 12V, the PFET is off (Vgs=0V).

As V(g) decreases from 12V toward ~11V (Vgs=-1V), the PFET begins turning on, pulling its drain V(d) toward +12V in-spite of the 6Ω load.

By the time V(g) reaches ~10V (Vgs=-2V), the PFET is turned on about as hard as it needs to be to deliver 2A to the 6Ω load resistor. Note the power dissipation in the PFET (the violet trace) as the gate voltage moves from 0V to -4V, which is the X-axis of the plot.

As the Vgs drive is increased (decreased?) from -1V to -4V, the PFET turns on better, reducing its Ron, and thereby reducing the power lost in the PFET.

In a subsequent post, I will show how to drive this from a micro pin that swings from 0V to 3.3V, but I want you to understand this post first.

Very interesting, thks!
Kudos to both you and dknguyen for your explanatory skills!

 

[dknguyen]

No, I am not sure at all: I just want to switch the 12V supply to the sensors on and of using a mosfet and a 3V microcontroller output. I did not realise your comment in the last paragraph.
So, a solution to switch 12V to the load represented by the sensors, driven by a 3V gate voltage would be very helpful.

You understand what I mean when I said there is no point using a PMOS on the low-side right? Because you might as well just use an NMOS which is better. You use a PMOS so you don't interrupt the ground path.

So in post #22, note where the gate, source, and drain pins are. It's flipped upside down compared to an NMOS in the same location. The important thing is to note that the the MOSFET turns OFF when the gate equals the source pin voltage (just like an NMOS), but unlike an NMOS, to do that requires the gate to be pulled to12V. The MOSFET starts to turn ON when the gate is pulled below 12V by a more than the threshold voltage and fully turns on if you pull it sufficiently farther below that. The most straightforward way to do this is to pull it to ground. So again, the greater the voltage difference between gate and source, the more the PMOS turns on, just like an NMOS. But unlike an NMOS the gate voltage needs to be pulled towards ground to do this.

 

[MikeMl]

So here is a practical PFET high-side driver that starts from a 3.3V swing coming out of a micro port pin:

The green trace is the signal from the port pin. In this simulation, it switches high at 20us and switches back low at 50us. It drives the gate of a small-signal NFET, whose Vth is about ~1V, near the center of the swing. Time is the X-axis.

M2 amplifies and inverts the signal to make V(d1) = red, and swings from +12V to 0V and back to 12V.

The voltage divider R1 and R2 constrains V(g)=blue to be between 12V and 6V, making Vgs of M1 either 0V or -6V (well within the max allowed).

Finally V(d2) = violet shows the voltage delivered to the 6Ω load R3. Note that is a max load current of ~12V/6Ω = 2A!

This driver turns on in ~2us, but it takes about 20us to turn off, mostly due to charge stored in the gate region of M1.

 

[audioguru]

The source of a P-channel Mosfet must be positive (you have +12V) and the drain has the load to ground. But it turns off when its gate is at the supply voltage (+12V) but the 3V microcontroller output does not go that high.

 

[earckens]

Great explanation! So a two stage drive is needed! Very clever. The first NMOS is used as a voltage multiplier for the PMOS.. genial. To audioguru, dknguyen and MikeMI: these forum posts I print out for future reference.

You understand what I mean when I said there is no point using a PMOS on the low-side right? Because you might as well just use an NMOS which is better. You use a PMOS so you don't interrupt the ground path.

So in post #22, note where the gate, source, and drain pins are. It's flipped upside down compared to an NMOS in the same location. The important thing is to note that the the MOSFET turns OFF when the gate equals the source pin voltage (just like an NMOS), but unlike an NMOS, to do that requires the gate to be pulled to12V. The MOSFET starts to turn ON when the gate is pulled below 12V by a more than the threshold voltage and fully turns on if you pull it sufficiently farther below that. The most straightforward way to do this is to pull it to ground. So again, the greater the voltage difference between gate and source, the more the PMOS turns on, just like an NMOS. But unlike an NMOS the gate voltage needs to be pulled towards ground to do this.

Ok, this and the drawing of post #22 and #26 are very clear, thanks for that!

So here is a practical PFET high-side driver that starts from a 3.3V swing coming out of a micro port pin:

View attachment 112587

The green trace is the signal from the port pin. In this simulation, it switches high at 20us and switches back low at 50us. It drives the gate of a small-signal NFET, whose Vth is about ~1V, near the center of the swing. Time is the X-axis.

M2 amplifies and inverts the signal to make V(d1) = red, and swings from +12V to 0V and back to 12V.

The voltage divider R1 and R2 constrains V(g)=blue to be between 12V and 6V, making Vgs of M1 either 0V or -6V (well within the max allowed).

Finally V(d2) = violet shows the voltage delivered to the 6Ω load R3. Note that is a max load current of ~12V/6Ω = 2A!

This driver turns on in ~2us, but it takes about 20us to turn off, mostly due to charge stored in the gate region of M1.

I am just a bit confused that the drain of M2 is called d1 and the drain of M1 is d2 but I got the xplanation. Why is the blue trace (M1 gate voltage) not following the red trace (M2 drain) between 20µs and 30µs?


I am gone for a 5 day vacation today, that will give me some time to let it all sink in: this is way better than I could have hoped for: thanks a lot for this thorough explanation. Next week I will get back here.

 

[dknguyen]

I am just a bit confused that the drain of M2 is called d1 and the drain of M1 is d2 but I got the xplanation. Why is the blue trace (M1 gate voltage) not following the red trace (M2 drain) between 20µs and 30µs?

What do you mean?

M1 gate between 20-30us is a curve because it's discharging the gate capacitor through a resistance. The gate capacitor's voltage is the voltage of the gate which controls the MOSFET.

 

[earckens]

What do you mean?

M1 gate between 20-30us is a curve because it's discharging the gate capacitor through a resistance. The gate capacitor's voltage is the voltage of the gate which controls the MOSFET.

Ok, I understand now.

 

[MikeMl]

.... So a two stage drive is needed! Very clever. The first NMOS is used as a voltage multiplier for the PMOS.. ..

The voltage gain is not that important; think of M2 as a level-shifter from the ground side to the +12V rail.

I am just a bit confused that the drain of M2 is called d1 and the drain of M1 is d2 but I got the xplanation.

That was just the order that I named the nodes in the schematic. I should have been more careful to make the reference designators increase from left to right, and likewise name the nodes in the circuit in a more logical order. All LTSpice cares about is that they be unique, not that they are in any particular order...

Why is the blue trace (M1 gate voltage) not following the red trace (M2 drain) between 20µs and 30µs?

First, V(g) comes from a tap on a voltage divider, so it is ratiometric with respect to 0V and 12V, hence while V(d1) swings 12V, V(g) swings only from 12V to 6V and back.
Second, the effective series resistance of the voltage divider R1 and R2 is charging and discharging the gate-to-source and gate-to-drain Miller capacitance of the PFET. Although 20us looks like a long time for the PFET to turn off, that is not very long if you are switching the load on/off a few times per second.

 

[earckens]

So here is a practical PFET high-side driver that starts from a 3.3V swing coming out of a micro port pin:

(...)

The green trace is the signal from the port pin. In this simulation, it switches high at 20us and switches back low at 50us. It drives the gate of a small-signal NFET, whose Vth is about ~1V, near the center of the swing. Time is the X-axis.

M2 amplifies and inverts the signal to make V(d1) = red, and swings from +12V to 0V and back to 12V.

The voltage divider R1 and R2 constrains V(g)=blue to be between 12V and 6V, making Vgs of M1 either 0V or -6V (well within the max allowed).

Finally V(d2) = violet shows the voltage delivered to the 6Ω load R3. Note that is a max load current of ~12V/6Ω = 2A!

This driver turns on in ~2us, but it takes about 20us to turn off, mostly due to charge stored in the gate region of M1.

As a replacement for the BSS123, would any of these do: SI2312, BSS138, AO3400A (datasheets annexed)?

And for the AO6407, would one of these do (nice to have a low on-resistance, but I only need to switch 200mA): FU9024 or AOD403?
EDIT (added): and maybe even an SI2301?

 

[earckens]

The voltage gain is not that important; think of M2 as a level-shifter from the ground side to the +12V rail.


That was just the order that I named the nodes in the schematic. I should have been more careful to make the reference designators increase from left to right, and likewise name the nodes in the circuit in a more logical order. All LTSpice cares about is that they be unique, not that they are in any particular order...


First, V(g) comes from a tap on a voltage divider, so it is ratiometric with respect to 0V and 12V, hence while V(d1) swings 12V, V(g) swings only from 12V to 6V and back.
Second, the effective series resistance of the voltage divider R1 and R2 is charging and discharging the gate-to-source and gate-to-drain Miller capacitance of the PFET. Although 20us looks like a long time for the PFET to turn off, that is not very long if you are switching the load on/off a few times per second.

Hi MikeMI, would it please be possible for you to have a look at my post #32 and give your opinion? I need it to decide on the package form for the PMOS component? Thank you!