Fpga

Status
Not open for further replies.
Last edited:
Looks like a good starting point for FPGA's, that first book you mention FPGA 101 I think I have that as an E-Book, I have a few E-Book resources about FPGA's, just haven't had a chance to look at them yet, if you want any let me know!
 
ah cool if you get a chance i would love to know if you think its a good book in the future...
 
Trying to create some blink code and get a crazy error:
Code: 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity BlinkLed is
	Port (
		led0 : out STD_LOGIC;
		clk : in STD_LOGIC		
	);
end BlinkLed;

architecture Behavioral of BlinkLed is
 begin
	synchronous_description : process(clk) is begin

			if rising_edge(clk) then 
			    led0 <= '1'; 
			else
				 led0 <= '0';
		   end if;
		
   end process;
end Behavioral;

My UCF file:
Code: 
NET "clk" LOC = "P89" | IOSTANDARD = LVCMOS25 ;
NET "led" LOC = "P86" | IOSTANDARD = LVCMOS25 ;

My Error:
Code: 
ERROR:Xst:827 - "C:/XWD/BlinkLED/BlinkLed.vhd" line 34: Signal led cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release.
 
i even tried without the "rising_edge(clk)" the long way... (change the variable names also)
Code: 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity BlinkLed is
    Port ( LED_01 : out  STD_LOGIC;
           OSC_IN : in  STD_LOGIC);
end BlinkLed;

architecture Behavioral of BlinkLed is

begin

	process (OSC_IN)
	begin  
		if (OSC_IN'event and OSC_IN = '1') then
			LED_01 <= '1'; 
		else
			LED_01 <= '0'; 
		end if;
	end process;

end Behavioral;

Still a no go
 
Ok the problem was:

"OSC_IN'event "

But why i cant use it is a mystery... really. What its used for is also a mystery heh. i assume its to tell me if the clocked changed states and the next item checks if the state is 1...
 
You code appears wrong. Try this:

...
if(rising_edge clk)
LED_01 <= not LED_01;

Make sure you initialize the signal. Try using a reset signal

...
if(rising edge clk or falling_edge reset)
if(reset = '0')
LED_01 <= '0';
else
LED_01 <= not LED_01;
....

something like that. My syntax may be a little off, long time since I wrote VHDL, but hope you get the idea...
 
For your simple example, you can get away without it -- in synthesis. But your simulation tools won't be able to simulate it correctly. Any sequential design you do that is more complicated, always use reset for initialization.

Here is a clean way to do it:

process(clk, reset) then
if(reset = '0')
...
elsif(rising_edge(clk)) then
....
end if;
 
Last edited:
Ok cool thanks, but just to let you know i have seen tons of designs without the use of it. But ill be sure to use it. I think i better understand it now also
 
I've seen tons of poor design practices too. Better to learn the right way out of the gate.
 
Last edited:
heh yeah thats true. Ok to be sure i understand...
This code synthesizes ok
Code: 
	process(OSC_IN, RESET) is begin --Handle the inputs
	if(RESET = '1') then  --if RESET is high then  set the LED to low (off in my case)
		LED_01 <= '0';
	elsif(rising_edge(OSC_IN)) then //If RESET is LOW and the RISING EDGE of clock is hit then turn LED on 
		LED_01 <= '1'; 
	end if;

How would i turn off the LED off when the Clock is LOW then ?

do i simply add after that ?

Code: 
--AFTER IT ADD
	if(OSC_IN = '0') then
		LED_01 <= '0';
	end if;

or

Code: 
--AFTER IT ADD
	if(falling_edge(OSC_IN)) then
		LED_01 <= '0';
	end if;
The below seems to synthesize ok and simulates fine
Code: 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity BlinkLed is
    Port ( LED_01 : out  STD_LOGIC;
           OSC_IN : in  STD_LOGIC;
			  RESET : in STD_LOGIC);	  
end BlinkLed;

architecture Behavioral of BlinkLed is
begin
	
	process(OSC_IN, RESET) is begin
	
	if(RESET = '1') then
	  LED_01 <= '0';
	elsif(rising_edge(OSC_IN)) then
	  LED_01 <= '1'; 
	end if; 
		
	if(OSC_IN = '0') then
	  LED_01 <= '0';
	end if;
		
	end process;

end Behavioral;
 
Last edited:
You don't trun off the LED when the clock is low. You turn it on and off on alternate clock periods, using this line as I've written above:

if(rising_edge(clk)) then
LED_0 <= not LED_0;
.....

on each clock edge, the LED will change states.
 
Last edited:
Take a look at the simulation image... As you can see when RESET is low it allows the LED to be controlled and when high even with a clock still coming in the LED is held low...

 

Attachments

  • sim.jpg
    20 KB · Views: 240
BrownOut said:
You don't trun off the LED when the clock is low. You turn it on and off on alternate clock periods, using this line as I've written above:

if(rising_edge(clk)) then
LED_0 <= not LED_0;
.....

on each clock edge, the LED will change states.
Click to expand...

Ah i see now.. cool thanks... since i didnt copy paste i missed that
 
If i do that then to synthesize i need to make the PIN inout type to be able to read the current state. Otherwise i get a error...

Here it is tho.. now i see what i was doing heh.. trying to change it on half a clock really.

 

Attachments

  • sim.jpg
    23.9 KB · Views: 226
Status
Not open for further replies.

Similar threads

T
PWM in Verilog - FPGA_Altera_Cyclone II
Replies
6
Views
4K
ronsimpson
W
Fpga/cpld?
Replies
11
Views
2K
Wilksey
W
Fpga ram
Replies
0
Views
2K
AtomSoft
Analog with FPGAs
Replies
5
Views
2K
Wond3rboy
A
Programing a Microcontroller with an FPGA board.
Replies
1
Views
1K
Nigel Goodwin
Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…