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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:32:16 08/08/2011
-- Design Name:
-- Module Name: BlinkRate - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity BlinkRate is
port( Button: in std_logic;
Clock: in std_logic;
Reset: in std_logic;
LED: out std_logic
);
end BlinkRate;
architecture FSM of BlinkRate is
signal Count: std_logic_vector(24 downto 0);
signal State: std_logic_vector(1 downto 0);
signal NextState: std_logic_vector(1 downto 0);
begin
SYNC_PROC:process(Clock, Reset)
begin
if ( Reset='1') then
State <= (others => '0');
Count <= (others => '0');
elsif ( Clock'event and Clock='1') then
Count <= Count + 1;
State <= NextState;
end if;
end process;
STATE_PROC:process( State, Button)
begin
case State is
when "00" =>
if( Button = '0') then
NextState <= "01";
end if;
when "01" =>
if( Button = '0') then
NextState <= "10";
end if;
when "10" =>
if( Button = '0') then
NextState <= "11";
end if;
when "11" =>
if( Button = '0') then
NextState <= "00";
end if;
when others =>
NextState <= "00";
end case;
end process;
end FSM ;WARNING:Xst:1306 - Output <LED> is never assigned.
WARNING:Xst:737 - Found 4-bit latch for signal <NextState>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:2677 - Node <NextState_0> of sequential type is unconnected in block <BlinkRate>.
WARNING:Xst:2677 - Node <NextState_1> of sequential type is unconnected in block <BlinkRate>.
WARNING:Xst:2677 - Node <NextState_2> of sequential type is unconnected in block <BlinkRate>.
WARNING:Xst:2677 - Node <NextState_3> of sequential type is unconnected in block <BlinkRate>.
WARNING:Xst:2677 - Node <State_2> of sequential type is unconnected in block <BlinkRate>.
WARNING:Xst:2677 - Node <State_1> of sequential type is unconnected in block <BlinkRate>.
WARNING:Xst:2677 - Node <State_0> of sequential type is unconnected in block <BlinkRate>.
WARNING:Xst:2677 - Node <State_3> of sequential type is unconnected in block <BlinProcess "Synthesize - XST" completed successfullywhen "00" =>
if( Button = '0') then
NextState <= "01";when "00" =>
if( Button = '0') then
NextState <= "01";
else
NextState <= State; STATE_PROC:process( State, Button)
begin
Next_State <= State;
case State is
when "00" =>WARNING:Xst:1306 - Output <LED> is never assigned.
WARNING:Xst:2677 - Node <State_3> of sequential type is unconnected in block <BlinkRate>.
WARNING:Xst:2677 - Node <State_2> of sequential type is unconnected in block <BlinkRate>.
WARNING:Xst:2677 - Node <State_1> of sequential type is unconnected in block <BlinkRate>.
WARNING:Xst:2677 - Node <State_0> of sequential type is unconnected in block <BlinkRate>.----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:32:16 08/08/2011
-- Design Name:
-- Module Name: BlinkRate - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity BlinkRate is
port( Button: in std_logic;
Clock: in std_logic;
Reset: in std_logic;
LED: out std_logic
);
end BlinkRate;
architecture FSM of BlinkRate is
signal Count: std_logic_vector(24 downto 0);
signal State: std_logic_vector(1 downto 0);
signal NextState: std_logic_vector(1 downto 0);
begin
SYNC_PROC:process(Clock, Reset)
begin
if ( Reset='1') then
State <= (others => '0');
Count <= (others => '0');
elsif ( Clock'event and Clock='1') then
Count <= Count + 1;
State <= NextState;
end if;
end process;
STATE_PROC:process( State, Button)
begin
case State is
when "00" =>
if( Button = '0') then
NextState <= "01";
else
NextState <= "00";
end if;
when "01" =>
if( Button = '0') then
NextState <= "10";
else
NextState <= "01";
end if;
when "10" =>
if( Button = '0') then
NextState <= "11";
else
NextState <= "10";
end if;
when "11" =>
if( Button = '0') then
NextState <= "00";
else
NextState <= "11";
end if;
when others =>
NextState <= "00";
end case;
end process;
end FSM ;
----------------------------------------------------------------------------------
-- Company: AtomSoftTech
-- Engineer: Jason Lopez
--
-- Create Date: 09:41:51 08/01/2011
-- Design Name:
-- Module Name: BlinkLed - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: Just blink LEDs
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity BlinkLed is
Port ( LED_01 : out STD_LOGIC;
OSC_IN : in STD_LOGIC;
RESET : in STD_LOGIC);
end BlinkLed;
architecture Behavioral of BlinkLed is
signal state : STD_LOGIC;
signal count : STD_LOGIC_VECTOR(24 downto 0);
begin
process(OSC_IN, RESET) is begin
if(RESET = '1') then
state <= '0';
count <= (others => '0');
elsif(rising_edge(OSC_IN)) then
if(count=16000000) then
state <= not state;
count <= (others => '0');
else
count <= count + 1;
end if;
end if;
end process;
LED_01 <= state;
end Behavioral;
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:32:16 08/08/2011
-- Design Name:
-- Module Name: BlinkRate - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.numeric_std.ALL;
entity BlinkRate is
port( BTNA: in std_logic;
CLOCK: in std_logic;
RESET: in std_logic;
LED: out std_logic
);
end BlinkRate;
architecture FSM of BlinkRate is
signal Count: std_logic_vector(24 downto 0);
signal Rate: std_logic_vector(24 downto 0);
signal State: std_logic_vector(1 downto 0) := "00";
signal NXT_STATE: std_logic_vector(1 downto 0);
signal LED_STATE : std_logic;
--signal BTN_STATE : STD_LOGIC;
begin
SYNC_PROC:process(CLOCK, RESET)
begin
if ( RESET='1') then
Count <= (others => '0');
LED_STATE <= '0';
elsif ( CLOCK'event and CLOCK='1') then
Count <= Count + 1;
if(Count = Rate) then
LED_STATE <= not LED_STATE;
Count <= (others => '0');
end if;
--State <= NXT_STATE;
end if;
LED <= LED_STATE;
end process;
STATE_PROC:process(State, BTNA)
begin
if ( BTNA'event and BTNA='1') then
State <= NXT_STATE;
end if;
case State is
when "00" =>
Rate <= std_logic_vector( to_unsigned( 32000000, 25 ));
NXT_STATE <= "01";
when "01" =>
Rate <= std_logic_vector( to_unsigned( 16000000, 25 ));
NXT_STATE <= "10";
when "10" =>
Rate <= std_logic_vector( to_unsigned( 8000000, 25 ));
NXT_STATE <= "11";
when "11" =>
Rate <= std_logic_vector( to_unsigned( 4000000, 25 ));
NXT_STATE <= "00";
when others =>
NXT_STATE <= "00";
end case;
end process;
end FSM ;WARNING
loads of these components. It is recommended that Top and Bottom BUFG sites be used instead of Side-BUFG sites
whenever possible because they can reach every clock region on the device. Side-BUFG sites can reach only clock
regions on the same side of the device and also preclude the use of certain Top and Bottom BUFGs in the same clock
region.
WARNING
completely routed in this design. See the "shift32.unroutes" file for a list of
all unrouted signals. Check for other warnings in your PAR report that might
indicate why these nets are unroutable. These nets can also be evaluated
in FPGA Editor by selecting "Unrouted Nets" in the List Window.
WARNING
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.numeric_std.ALL;
entity shift16 is
Port ( SI : in STD_LOGIC;
SC : in STD_LOGIC;
SR : in STD_LOGIC;
DB : out STD_LOGIC_VECTOR (15 downto 0));
end shift16;
architecture Behavioral of shift16 is
signal tempReg : STD_LOGIC_VECTOR (15 downto 0);
begin
process (SC,SR)
begin
if(SR = '1') then
tempReg <= (others => '0');
elsif(SC'event and SC='1') then
tempReg <= tempReg(14 downto 0) & SI;
end if;
end process;
DB <= tempReg;
end Behavioral;
