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PWM in Verilog - FPGA_Altera_Cyclone II

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taher1983

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Hi,

I need some help regarding the steps required to design a digital system to produce a PWM signal that produces pulses at a frequency in the range 50Hz-100Hz. The pulses will be between 1ms and 2ms duration. The actual length of the pulse will be determined by a person's name. The 1ms variation in pulse length is to be controlled by the ASCII value of the name's initials (https://www.asciitable.com/). After the first ms of the pulse the remainder of the pulse will be determined by the ASCII value of the initials. This means that the ASCII value determines the length of the pulse is that after the first ms of the remaining length should be: asci value / 256 x 1 ms. I need to produce a system that generates two pulses whose lengths are determined by first initial then two pulses whose lengths are determined by second initial, then repeating back to first initial. The system should have an input that allows you to change whether it is using the uppercase value or the lower case value of initials. This has to be done in Cyclone II FPGA using Verilog. i have a basic understanding of PWM as well as Verilog but am not that strong in HDL coding, help please.
 
Hey taher1983 !
I am currently trying to replicate something similar to what you were hoping to find an answer for and was wondering if you had managed to find a solution? Any help would be great.
Thanks
 
Break the project down into little pieces.

You can see there needs to be a ASCII receiver. (UART) There should be lots of examples on the internet. Most UARTs 16x over sample. You can build one that 2x over samples. You need to get two ASCII charters and hold them in a register.

256 x 1 ms
It looks like you need a clock that is 256khz. Did I do that right? In 1mS you need to have 256 clocks.
I think you need a 9 bit counter.
At "time-0" set the output.
At count = 100 hex + ASCII_Value, reset the output.
At time = 1FF hex reset the counter and wait.
(bit 9=1, bit8:1= ASCII_Value)
This should out put 1 for 1mS + Value.

It looks like ASCII_Value needs to "mux" between Value_first and Value_last.

Just build something and see what happens. Example: build the UART and bring the 8 output out to LEDs and see what happens.
 
ronsimpson
I have done a lot of research and looked at what you were proposing and feel I understand what I am meant to do slightly better. In particular, I found a very helpful tutorial on verilog programming of a PWM signal. Since you seem well versed in what you are talking about, I wondered if you could tell me if this tutorial is along the right lines of what I want to create? Just so I know I'm not barking up the wrong tree.
https://www.fpga4student.com/2017/08/verilog-code-for-pwm-generator.html
Also, you mentioned building a UART which was a concept I was unfamiliar with. After looking them up, they seem quite complicated to produce. (I wouldn't have thought our lecturer would give us something that complex since the most complex discussion in lectures has been about programming simple finite state machines).
 
I second your concern that a UART is not beginner-friendly. In that spirit, here is a canned implementation.
As to the referenced Verilog PWM-code: it looks like it could be the basis for your work, but there is a lot remaining to do.
- the frequency is 10MHz and you want 50-100Hz. You will need a clock-prescaler and clock-enables.
- some means (perhaps a lookup table?) to convert letter-values to pulse-durations
- a state-machine to remember the first AND second letter-values

... and lots of other things.

What/how much have you done so far?
 
UART is not beginner-friendly
A UART can be hard but:
Find out what your PC is doing and only decode that. Pic a speed like 9600 or 110 and stay with that. (clock frequency must be good 1% or better)
Pick 6, 7 or 8 data bits.
I have seen FPGA USRTS that run at 2x but most run at 16x clock to data rate.
On falling edge start your state machine.
Wait 1/2 time to get to the center of the data window.
Wait 1 time to get to D0. Now use a shift register to store 8 bata bits.
Test for STOP condition and reset your state machine. (store data)
**broken link removed**
See it is simple.
See picture. Usually there is a long delay between STOP and START.
 
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