Flipflop counter

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I have a pulse as a input of a counter will u plz suggest me the counter design.
The ckt should work like this:
when the is first positive and then negative it should up count
when the is first negative and then positive it should up count
PLZ ONLY USE FLIPFLOPS
 

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count UP when input pulse is +-
count DOWN when input pulse is -+???
 
look @ diagram i have designed a counter whose output is like this.
When an object is entering the pulse is exactly as shown in the figure.That pulse is given by my sensor ckt and this ckt gives exactly opposite pulse when the object leaving is leaving.
Entering->counted up
leaving->counted down..
plz help........
 
Gotta love it when people say they have designed things but really want you to do all of the designing.
 
Which logic family are we talking about? The only flip-flops I am familiar with are edge triggered -- period. Did you come up with this marvelous design in the margins of your favorite SF novel?
 
Someone is confussed or ??

when the is first positive and then negative it should up count
when the is first negative and then positive it should up count
when the is first positive and then negative it should up count

[COLOR="Teal"when the is first negative and then positive it should up count][/COLOR]
they both count up??
only way I see is to use a couple of gates as inverters
 
solution provided

Which logic family are we talking about? The only flip-flops I am familiar with are edge triggered -- period.
Actually, PLS is pretty much based on set/reset flip-flops. And it's fairly possible to make out a counter (ok, wee need aditional D-flipflops too for counting function) out of it.

Have a mix of a capacitor input to sense negative pulses, and you'll be on right track
 
The only thing I've EVER used SR flip-flops for is pushbutton debouncing. I don't even do that anymore, since doing it in firmware is much more robust. I'm primarily a JK designer.

I am not familiar with PLS; could you expand the acronym? I Googled it and came up with a lot of nothing. Did you mean PLC? That's what Google asked me.

It almost seems as if we are talking about ternary logic, or logic with three levels, positive, ground, and negative. Is this the case? I can envision a state machine that would accumulate pulse pairs and count up or down. Is there a separate clock signal that we are using to sample the pulse trains, or is a clock generated for each pulse pair?
 
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Agreed. What ElectronicsDevil needs to do is show us a schematic of the circuit which produces this bipolar waveform. A more useful waveform may be available. I suspect that this is a school assignment since only flip-flops can be used.
 
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