Multiple flipflop (piano switch)

[GrahamR]

Hi all.
I thought this would be a straightforward development from a "two-key piano switch", ie an ordinary flipflop, but it's got me baffled, which admittedly doesn't take much.
I can't find anything online. Is it so easy that nobody's bothered posting it? Or am i searching for the wrong thing?
Thanks very much,

 

[danadak]

If the cap is charged thats when the potential problem occurs if Vcc is removed and it rapidly collapses
>> faster than the RC discharge you mentioned.

Did you notice the web has many studies with varying time, or the fact that ap note had a clean
clock, which you dont ? ChatGPT shows times :

Would seconds be a problem in this design ?

Lastly KISS = Keep It Stable and Simple should apply.

 

[rjenkinsgb]

Would seconds be a problem in this design ?

The metastable state in the TI document refers to the data level being in transition at the same instant as the clock, a few nanosecond level timing coincidence. That can leave the data bistable in a mid-transition balanced state, which then takes time to resolve itself.

The data to clock delay in the switch circuit is milliseconds. How on earth is that type of metastable coincidence relevant to this circuit?? You seems to be clutching at straws here

 

[crutschow]

If the cap is charged thats when the potential problem occurs if Vcc is removed and it rapidly collapses
>> faster than the RC discharge you mentioned.

As I stated, the capacitor is only charged during the short time the PB is pressed.
What do you think the chances of that occurring exactly when the power is removed?

Would seconds be a problem in this design ?

It would.
But your reference said that occurrence is "extremely rare", so doesn't sound like a significant issue to me.

 

[danadak]

As I stated, the capacitor is only charged during the short time the PB is pressed.
What do you think the chances of that occurring exactly when the power is removed?

It would.
But your reference said that occurrence is "extremely rare", so doesn't sound like a significant issue to me.

What are the chances...., only one event needs to burn out part......but go with your design
methodology risk avoidance minimization. Note only takes R between cap and pin to take
care of issue, but then that apparently would break your design methods and so I fully
support you doing it your way.

But your reference said that occurrence is "extremely rare", so doesn't sound like a significant issue to me.

Go for it.....ignore the reference that I added seconds have been observed in other investigations.

 

[danadak]

The metastable state in the TI document refers to the data level being in transition at the same instant as the clock, a few nanosecond level timing coincidence. That can leave the data bistable in a mid-transition balanced state, which then takes time to resolve itself.

The data to clock delay in the switch circuit is milliseconds. How on earth is that type of metastable coincidence relevant to this circuit?? You seems to be clutching at straws here

That circuit timing guaranteed to have mS of delay, huh, so you have timing control of the button
event as related to clock timing, now I understand...... I stand with following vendor recommendations
and industry findings into Metastable behavior. Those are my straws.

 

[crutschow]

Go for it.....

So glad you approve.

 

[danadak]

More info on large C tied to pins as well as slow Tr/Tf times causing
internal and external unwanted transients. Attached.

Another thread on the topic :

Large C connected to CMOS Inputs

Folks seem to like building delays, debounce keys, etc, by placing large C at the inputs to CMOS gates. NOT A GOOD IDEA For case where supply collapse rapid due to its design, load situation. TI confirms this in an ap note on general CMOS usage. Here is a rough sim of the problem. Note since...

www.electro-tech-online.com

Regards, Dana.