What is the problem?

[mindhacker]

I am about to make a perfect D flip-flop out of simple gates. I used 74ls00 as illustrated in the diagram. It works perfectly alone but when i connect its input to a circuit it started to work incorrectly. Example is this. I connect its Q' to its D input. Q is supposed to be 0 then 1 then 0....but it works indefinitely. As if it is in undefined state What causes this? How can I fix it?

 

[ljcox]

It sounds like a timing problem.

Look at the IC data sheet & calculate the delays of each path for each state and see if there are any timing races.

 

[mindhacker]

what should i do? e=clock and i am using a clock pulse generator that has diff frequency controlled by a potentiometer.

 

[ljcox]

You can do one of two things:-

Do what I suggested in my previous post or,

Buy a D type Flip Flop.

 

[mbarazeen]

there is some thing wrong in your connection, when Q' is low that is connected to D input, when E goes high imediately Q' comes high and D goes low, this has to be prevented.

Edit: you have to add another latch stage driven by inverted clock input to enable it and take the feed back from that output. see the attached pic

 

[mindhacker]

It is not working. When the clock is high Q and not Q' are both high. Maybe this means that the rs is in racing condition?

 

[mbarazeen]

did you check the one i posted? in your circuit you are allowing both inputs to go high simultaniously by your feedback and its not allowed. you get 1 in both out put, you may be right, i beleive your latch is oscillating with high frequency.

you have to make an intermidiate latch as i suggested to hold the feed back until the clock goes high/low

 

[mindhacker]

how? can you show me how?

 

[Gary B]

The only problem with the original is that the input stage gets a clock to each gate, D input to one gate and D NOT to the other input. The out put of this section connects directly to the input of the RS section without any type of crossover.

 

[mindhacker]

so i should and the output q' and the clock before i input it to D?

 

[mbarazeen]

how? can you show me how?

see the attached timing diagram

 

[Gary B]

D ff

This is the most straight forward version of a D Flip Flop I have encountered. The state of D is transferred to Q One clock transition later. Sorry about the quality of the drawing but I have to use Paint since I can’t load foreign programs onto my system.

 

[mbarazeen]

This is the most straight forward version of a D Flip Flop I have encountered. The state of D is transferred to Q One clock transition later. Sorry about the quality of the drawing but I have to use Paint since I can’t load foreign programs onto my system.

you are right, this is the common way when your input is external and the input only changes when the clock is low. the OP needs to utilise the out put fed again to the input, that is where the problem is.

 

[Gary B]

Connect Q NOT to D. the first half of the above is different than any of the other configurations above.

 

[mindhacker]

I have tried everything you said using 74ls00 but it doesnt work. grrr. but when im using the real D f/f ic which is the 74ls175 it works perfectly.

 

[Gary B]

Then I guess it is time to pull the drawing of a 74LS175 and check out the difference in the two circuits. The one I posted was from the web and was the simplest form. There is another configuration that uses 7 gates total including one set up as an inverter that allows preload and reset. It uses 3-input NAND gates in most locations.

 

[mindhacker]

but its just symbol also.

 

[ericgibbs]

but its just symbol also.

hi,
It works in LTspice simulation, a low value capacitor has been added to stop the circuit from oscillating at start up.

 

[mindhacker]

oh thats interesting ill try it at home

 

[mbarazeen]

hi,
It works in LTspice simulation, a low value capacitor has been added to stop the circuit from oscillating at start up.

ericgibbs, the OP needed to have a divide by 2 counter by looping the out put to the input, where he struggled.