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TTL waveshaping, RC networks

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Positive Logic means what combination of the inputs cause the output to be HIGH?
Negative Logic means what combination of the inputs cause the output to be LOW?
 
What is DC component?

At my work , they say DC component is the "TIME GAP" or " Cross over" section between the positive and negative cycles at the zero crossing point when you have a push pull network

Is this Time gap or Cross over called DC component?
 

MrAl

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Most Helpful Member
Thanks for you info.



Yes, I have seen this, one clock signal is 180 degrees out of phase with the other one.

Any reason why they want the clock signal to be 180 degrees or have a 2 phase clock signal?


So inverting the logic state, turns a Positive logic truth table into a Negative truth table?

So A sine waveform has no slew rate?

They use Non-Inverting Schmitt triggers to convert a sine wave into a square waveform.

What's the difference between using an op amp to convert a sinewave into a square waveform or using a non-inverting schmitt trigger?

I have seen circuit that use either op amp or non inverting schmitt trigger to convert a sinewave into a square waveform but what is the difference between using an op amp or using a non-inverting schmitt trigger?

Hello again,

There are a lot of reasons for wanting a two phase clock, usually related to the timing of the other parts of the circuit where we need 1/2 clock timing. An example would be for using memory in an interlaced manner to achieve a 2x clock rate.

Lets look at the AND truth table again:
a b c
0 0 0
0 1 0
1 0 0
1 1 1

and the OR truth table:
a b c
0 0 0
0 1 1
1 0 1
1 1 1

If we invert all the zeros and ones in the OR table we get:
a b c
1 1 1
1 0 0
0 1 0
0 0 0

which is the AND table rearranged a little. So yes, inverting the inputs and outputs inverts the logical connective. So that's one way of looking at negative logic. It's not that hard however to just look at the zeroes instead of the ones.

A sine wave has a varying slew rate. The most important slew rate is at the zero crossing where it is maximum. That's the most important in op amp circuits.

Schmitt Trigger gates (inverting or not) are usually faster than op amps, but probably more importantly they are made to work with a certain logic family, unlike an op amp of any kind. This means they are well suited to performing that function whereas the corresponding op amp circuit has to be designed very carefully.
 
and the OR truth table:
a b c
0 0 0
0 1 1
1 0 1
1 1 1

If we invert all the zeros and ones in the OR table we get:
a b c
1 1 1
1 0 0
0 1 0
0 0 0
Yes this is how I looked at negative logic truth tables

What is the other ways of looking at negative logic please? u said there is other and more ways of looking at negative logic
 

MrAl

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Most Helpful Member
Hello again,


Well i think i said already that you just have to look at the zeros. If you look at the zeros of the OR gate you see an AND gate, where it takes two zeros to get an output that is zero. Normally we seem to look at the 1's and see that (AND gate) it takes two 1's to get a 1 on the output. That's looking at all the ones. But looking at the zeros helps too because then we see the 'other' gate which is the complement logic (ie AND to OR).
 
looking at the zeros helps too because then we see the 'other' gate which is the complement logic (ie AND to OR).
The hard part for me, is figuring out the other gate the complement logic

You must know the truth tables by heart
 

MrAl

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Most Helpful Member
Hi,

Why is that hard? If you look at the zeros, you can see that the only case where we get a zero output is when both inputs are zero (OR gate).

Is there something that is not clear, maybe we could figure this out and get to the bottom of it.

There's also the view where we just invert everything like you noted. Using a little math, we get:
c=a*b
c'=a'+b'

Here a single quote means to invert. Note that when we invert the logical connective "AND" we get the "OR" function instead. So we are inverting the function itself as well as the inputs and outputs. But rather than write *' (inverted AND) i just wrote the result which is + (which stands for OR).
Sometimes the AND function is just written without a sign like this:
c=ab
 
oh ok thanks

What are some common things to look for when troubleshooting on a logic analyzer?

Mostly when I used at work a logic analyzer was to look for if all the logic signals were in sync starting at the same time, had the right time intervals apart from each other, pulse widths were correct, lead and falling edges looked sharp and not rounded or slanted.

Anything else u can ad please that you visual inspecting logic signals using a logic analyzer?
 

MrAl

Well-Known Member
Most Helpful Member
Hello again,


A logic analyzer helps to show the various states of the circuit at progressive times. Thus it has wide application and the interpretation depends highly on the circuit being looked at.
If you have an AND gate you look at the inputs and outputs to make sure that the signals all follow the correct logic pattern, that as AND truth table would show you. It's that simple.
If you have two logic states that are close to each other but not exact and those signals are later processed you could end up with what we call a glitch. A glitch is a signal that is generated when the logic states occur close to each other but not exactly at the same time, yet the circuit after that assumes that they are going to occur at the very exact same time. That means a really fast pulse is generated and that could wreck havoc on the rest of the system. So that's another thing to look for.

Of course you check the timing of the circuit too, to make sure the signals occur at the expected times.
 
So mostly you checked for glitches?

Glitches are nanoseconds time delay between 2 logical signals?

Of course you check the timing of the circuit too, to make sure the signals occur at the expected times
What kind of timing signals have you seen what are bad or was causing problems?

What did you check for when checking the timing of the circuit? what are some things you check for in the timing signal?
 

MrAl

Well-Known Member
Most Helpful Member
Hi,


Well one problem that comes up is related to the propagation delay of a logic element such as a gate or flip flop.

The simplest example is if we wire up 10 logic gates in tandem where each gate has a propagation delay of 10ns, the total time for the input signal to reach the output is approximately 100ns, which is 10 times a normal gate delay. Now say we have a second circuit with only one gate, the total delay of that circuit is only 10ns. Now say we drive both inputs of the two circuits with a logic pulse who's duration is 110ns, and say we use a two input AND gate where we get the two inputs from the two circuit outputs, and we look at the output of the AND gate.
What we see is one circuit output takes 100ns to go high while the other circuit output goes high after only 10ns, so for the first 10ns nothing happens, then the second output goes high but that's only one input to the AND gate, then 90ns later the other circuit output goes high so finally after 100ns we have two highs on the input of the AND gate so the AND gate output (which also has a delay of 10ns) will go high 10ns later. So finally at 110ns later the AND gate output goes high. Then the input goes low again. The 10ns circuit gate output goes low at 120ns, then 10ns later at 130ns the output of the AND gate goes low again, and stays there.
So we ended up with an output that went high at 110ns, then went back low again after 130ns, so the output pulse was only 20ns wide.
Now if we had not considered the gate delays, we would have assumed that the two inputs translate to the outputs immediately and the result of the AND appears immediately at the output too. So thinking in these terms, the output would go high at t=0 seconds, and low again at t=110ns, following the input pulse exactly.

So you can see the difference there. 110ns vs 20ns, depending on if we considered the gate delays or not. So understanding the effects of the gate delays is important and testing for this may be necessary at some point too.

Another example is with flip flops connected in a ripple carry fashion. That's where the output of one FF triggers the clock of the next FF in the line. Say we have 32 stages, and the delay is 10ns for each stage. When the first clock triggers the first flip flop, the Q goes high after 10ns. But when the second clock triggers the first FF again, the Q goes low after 10ns, and that triggers the next stage flip flop, but the second FF output Q does not go high for ANOTHER 10ns, so the total delay is twice that of one FF, just like with the gates, but now it only happens during certain states. Unfortunately, if we have 32 flip flops all connected as ripple through counters, that means we have 32 times the delay when the last stage output Q goes low. That's 32 times 10ns or 320ns, and that is considerably longer than we might expect.
The problem here is not the delay itself, but it's effect when it is compared to other parts of the system that operate in parallel rather than in series like that. For example, if we had a set of eight 4 bit latches where we wanted to capture the total count in the FF's at any given time, we'd have to be careful about when we clock the latches (that's when they store the information of the FF's). If we clock it immediately after the last input pulse to the counters, we would actually end up latching the state of the counters BEFORE the last counters had a chance to change state, so we'd be capturing the counter states in the past. But unfortunately it's even worse than that, because some of the counters may have gotten a chance to change state, so we'd be latching an invalid state of the counters. Invalid not to the logic itself, but to the applications requirement.
I've seen this actually happen and the result is a bogus count is collected and displayed.

So one test would be to check the propagation delays of various parts of the circuit to see how they affect the system. During the design phase you always have to be aware of these kinds of delays though. Sometimes the delays are put in there on purpose to achieve some timing goal, but i dont believe that's the best design practice unless it is really necessary.

There's also the tests just to see that the logic is behaving normally. In this case you examine the circuit to determine what SHOULD be seen on the outputs, and then measure what really IS on the outputs, then compare results. That turns up problems too if there are any failed gates, shorts, etc.

I cant help but mention one other very interesting problem that comes up.
Some logic families have outputs that have lower impedance for a 'low' output than for a 'high' output. What this means sometimes is that an output can pull another high output low, but another high output can not pull another low output high. This means test patterns have to be created very carefully depending on the logic family. For example, testing outputs by setting them all to 1's or all to 0's doesnt work because if any pins are shorted you will never detect that, but more to the point, using a pattern of 8 bits of 10101010 isnt enough either because if the second and fourth output on the device package are shorted on the PC board, you'd never detect that. And ditto for 01010101 because that doesnt help either.
 
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So how do you know what is GOOD propagation delay VS BAD propagation delay?

Visually looking for bad propagation delay on a logic analyzer, one or more signals is going to be shifted in time , nudged in time, offset in time , that's what bad propagation delay looks like

When Logic signals are not in sync together that is bad propagation delay

Bad propagation delay is when the input gates are triggered X number of nanoseconds behind

Using a logic analyzer you have to measure the 2 or more inputs on a gate, and measure the propagation delay for both inputs which are nanoseconds from each other, is this right?

How do you measure propagation delays on a logic analyzer or on a digital oscilloscope?


This means test patterns have to be created very carefully depending on the logic family.
What you mean by test patterns? for CMOS and TTL?


When troubleshooting Analog or Digital circuits, What frequency and waveform do you set the function generator at mostly?

I set my up for sine waveform at 1Khz when injecting a function generator signal into a component to make sure its working right.

Using a Square waveform at 1Khz is better for troubleshooting , because if the square waveform has rounded edges or is slanted top or bottom , leading edge and falling edges are skewed , than it's a bad capacitor

What do you use a square waveform on the function generator for when troubleshooting using a square waveform?
 

MrAl

Well-Known Member
Most Helpful Member
Hello again,


Lets take one question at a time here :)

To test directly for propagation delay time, you could use a scope on the inputs and output. Looking at the time that the input signal occurs, and the time it takes for the output to respond. Often the 10 percent and 90 percent wave amplitudes are used as the thresholds for measurement.
To know if it is too long, we refer to the data sheet. If it says 10ns with 10pf load capacitance for example and we are measuring 50ns then we know something is wrong.
 
oh ok so you just use the data sheets

Often the 10 percent and 90 percent wave amplitudes are used as the thresholds for measurement.
Do you have to set up the logic analyzer for 10 percent to 90 percent amplitude?

How do you test the thresholds for measurement? Is it the a menu in the logic analyzer u have to set it up for this type of measurement to measure the threshold amplitude?
 

MrAl

Well-Known Member
Most Helpful Member
Hello,

That's for when you use the scope. You look at the point where it crosses the 10 or 90 percent point (of the max amplitude) and use that as the switch point.
 
That's for when you use the scope. You look at the point where it crosses the 10 or 90 percent point (of the max amplitude) and use that as the switch point.
Which menu do I go to on the o-scope to set it up for 10% to 90% points? I'm not sure how i set up my o-scope for this measurement

Do you measure I sure the Amplitude Cursors and set one up for 10% and the other for 90% point?
 

MrAl

Well-Known Member
Most Helpful Member
Hello,

You dont even have to do that really. Just look for the points where the wave goes through approximately 10 percent and 90 percent of the max amplitude.
 
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