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TTL waveshaping, RC networks

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The output of U8 pin#6 , the shark fin waveshape goes to U10 pin#6 SET input

Why is the waveshape a sharks fin? the RC network changed the waveshape from a square waveform to a shark fin

But why was this waveshape used?

U8, R39, C9 picture#1.jpg
 
Look at this rectified waveform on U5 output pin#1
Is the DC offset at 5 volts?
Or is the DC offset at 7.5 volts?

Rectified Waveform, DC offset at 5 volts.jpg

Or is the DC offset at 7.5 volts?

Rectified waveform, DC offset at 7.5 volts.jpg
 

audioguru

Well-Known Member
Most Helpful Member
The output of U8 pin#6 , the shark fin waveshape goes to U10 pin#6 SET input

Why is the waveshape a sharks fin? the RC network changed the waveshape from a square waveform to a shark fin
That is what the RC does.

But why was this waveshape used?
To produce a time delay.
 
First waveform is 1.48mS
Second waveform is the shark fin is 8msec.

Do you know why the time delay was used? for what reason?

Does the waveshape trigger the flip flop differently than a square waveform?

when using different triangle waveshapes for the inputs to logic gates or flip flops, what does it do different than using square waveforms/pulses waveshapes?

1.) It gives you less ON time and a exponential decay OFF time

But what does that do to the logic?

Why would the logic signal source need to have a time delay RC network or a waveshaped to be triangle or shark fin to the inputs of a GATE or flip flop, etc?
 

Brevor

Member
Do you know why the time delay was used? for what reason?Does the waveshape trigger the flip flop differently than a square waveform?Why would the logic signal source need to have a time delay RC network or a waveshaped to be triangle or shark fin to the inputs of a GATE or flip flop, etc?
We need to see the rest of the circuit to answer those questions.
 

Brevor

Member
Ok it looks like that circuit monitors a 3 phase power line. The outputs of the phase detectors are OR'd together in the 4025 NOR gate. If any phase is lost the output of the 4025 sets a latch to indicate the loss. The RC network delays the pulse to set the latch, this is probably so it is not triggered by short power fluctuations. The latch will trigger at a specific voltage level on the input, the ramp (shark fin) waveform just delays the voltage change on the input pin so it triggers a bit later.
 

MrAl

Well-Known Member
Most Helpful Member
Hi,


Looks to me like that section detects a loss of all phases. If we look at U10 the Set input takes a logical high as true, so that means the three input 'NOR' gate actually functions as a negative logic 'NAND' gate. That condition will light the LED.

But as far as the RC network, i agree it is probably there to prevent very short transitions or noise from setting the FF and thus turning on the error LED.

BTW those jpg files do not have to be that large to be clearly readable. A max of 2000 pixels of either dimension (width or height) is good enough. Bigger files take too long to download even on a fast connection because the site limits the transfer rate.
 
that means the three input 'NOR' gate actually functions as a negative logic 'NAND' gate
What do you mean how a NOR gate is functioned like a negative logic NAND gate, how so ? and why did the designer do this? Instead of using a NAND gate, because he used a NOR gate, why didn't the designer just use a NAND gate?
 
If a GATE or Flip flop is not working , what can I use to apply a +5 volt signal with to use as a logic signal source?

1.) A wall wart set at 5 volts, but how much current can I inject into a TTL and CMOS logic chips? Wall warts have high amps
2.) A power supply set at 5 volts, but how much current? I don't want to damage the TTL and CMOS logic chips
3.) What else can I use as a logic signal source?
 
What logic signals do you have to use the Oscilloscope with?
1.) Clock Signals
2.) What else

Most of the logic signals are just low and high voltages, so you mostly use your DVM 99% of the time right?

What other logic signals Pulse from high to low besides clock signals?
 

MrAl

Well-Known Member
Most Helpful Member
What do you mean how a NOR gate is functioned like a negative logic NAND gate, how so ? and why did the designer do this? Instead of using a NAND gate, because he used a NOR gate, why didn't the designer just use a NAND gate?

Hello again,


The decision to use an AND or OR or NAND or NOR depends on the logic signals that are already there before you decide, and what kind of output your gate needs to produce.
Im sure you've read about logic "True" and "False". True can be a high '1' or a low '0' and then False is the opposite. And you can have a true as a 1 in some locations in the circuit and true as a 0 in other locations. It all depends on what is the simplest solution when you go to design it.

In this circuit the designer had three signals that he wanted to check, those are the input signals to the NOR gate. It's drawn like a NOR gate because that's probably the kind of gate that it is advertised as being. When you go to buy one, you look for a "three input NOR gate". But the advertised name always follows the "positive logic" convention, in that it's name refers to what it would be called if it were used as a positive logic gate.

Using this gate as a positive logic gate, we would say that any single input that goes to a high state would cause the output to go low. So if we needed that kind of function, we would use this gate. Any input that goes high gives us our desired low output.

But what if we wanted a high output instead? Then we would use an OR gate. Any of the three inputs going high then causes a high output.

But wgat if we wanted to detect all three going high at the same time and provide a low output? Then we would use a NAND gate because then we would only get a low output when ALL THREE inputs went high. Otherwise we'd get a low output. So we'd be detecting all three simultaneously going high, not just one as with the other gates so far.

But that's not the end of the story either. What if we wanted to detect all three inputs going LOW instead of HIGH as before, and provide a HIGH output when this happens? Then we would need to use a NOR gate. With this kind of gate, the output only goes high when ALL THREE inputs are LOW, not high. So now we are looking for all LOW's on the inputs not highs. So we can say that the gate is a logical AND gate for the low signals, because input 1 AND input 2 AND input 3 all have to be LOW before we get our required output of a HIGH, and that output sets the following flip flop. That's the action we need, so we can call it a negative logic NAND gate. It's only drawn as a NOR gate because that's the way it is advertised and cataloged, but you can use it as a positive logic NOR gate or a negative logic NAND gate.

As far as measuring the signals, you can use a meter for static signals that do not change very fast. But when you need to see fast changing signals you need to use a scope. The inputs to that NOR gate above may require using a scope to see properly.

There are also test equipment known as Logic Probes. These devices have various functionality depending on how expensive they are. Some of the simpler ones detect a high and low with an LED or two, and some detect a Clock signal but dont show the wave shape.

It appears that if that section is working right the LED will light when you loose all three input phases. You can try testing for that if possible. To check the actual RC network you'd have to use a scope or pull one lead of each device (being careful not to wreck the component) and check the resistor with an ohm meter and the cap with a cap meter. Alternately buy those two parts, check them, then replace them on the board regardless if you suspect them.
 
For static logical signals, I use a DVM

For Clock signals and Reset signals, I use an oscilloscope to see the waveshape

When looking at a schematic and seeing different gates, how do you know if the designer is using the gate as a positive logic gate or a negative logic gate?

It's hard for me to tell is the logic is positive or Negative , how does a tech know?

Example: You can use a NOR gate either way
a positive logic NOR gate or a negative logic NAND gate.

What other examples do you know please?
 

MrAl

Well-Known Member
Most Helpful Member
Hello again,


For gate outputs it depends on what the gate output has to drive.
For gate inputs it depends on what the gate has to detect.

For example, say we have a light bulb we want to turn on when two logic signals BOTH become equal to a high (ie a '1'). That is only considering the inputs to the gate, and we also need to consider the output and what it has to drive, so say we connect the bulb from the output of the gate to ground. That means we need the output of the gate to go high (say it is 5v) to turn on the bulb because the other end of the bulb is connected to ground. Because we need both inputs to be high for this to happen, we use an AND gate because when both inputs to the AND gate go high the output goes high, and that's the only way the output can go high, so that does it.

Now say we connect the bulb from the output to +5v instead. Now we need the output to go low instead of high, so we use a NAND gate instead. When both inputs go high, the output goes low and that lights the bulb.

But say we already have an existing system and somewhere in that system we have two signals that go low and we want to know when they BOTH go LOW instead of both going high. Now we need a gate that can detect two low signals and provide an output to drive the bulb to light it up. Lets again say we connect the bulb from the output of the gate to ground. That means we need a high output signal to turn it on, and only when BOTH inputs go LOW. We know that if we take an OR gate if either input is high we get a high output, but that's not what we want, because we only want the bulb to light when we have BOTH inputs LOW. So if we invert the output of the OR gate we get a NOR gate. Now when EITHER input goes high, the output goes low, which is nice because that keeps the bulb off. Now it takes both inputs going LOW to make the output go HIGH to turn the bulb on. So what is happening here?
It turns out that with digital logic there is such a limited number of signal combinations that can appear at the input that there ends up being two ways of looking at it:
1. When the NOR gate gets EITHER input being a 1 the output will be LOW.
2. #1 means that since either input high can keep the output low it takes both inputs being low to make the output go high, and turn on the bulb.

#1 is the positive logic view, #2 is the negative logic view. Note that nothing changed in the circuit itself, but the way we look at the situation changed because of what we needed in the real world: to light the bulb for some input conditions and not light the bulb for some other input conditions.

So the way to tell how it is used is to find out what function it performs in the circuit, such as an error detector or phase detector or undervoltage detector or whatever else we might find in the circuit. And notice it has nothing to do with the actual circuit itself because it works the same way no matter how we look at it, it's just a different way of thinking. The designer was thinking of lighting an LED (and keeping it lit) if and when all three phases go away (some low voltage level) so he used whatever was the most convenient for the circuit that was already designed up to that point.
Note that had there had been three signals that went high when we wanted the LED to light up then he would have had to use an AND gate so that it would detect three high level logic signals rather than three low level signals.

Examining that part of the circuit where the gate is located helps to identify what the gate is actually doing. Sometimes it means tracing the circuit through several stages to understand that entire part of the circuit.
 
Thanks for you info

What circuits or stages uses negative logic? that is simple common circuits or you know of?

What would a designer use an Inverted Clock signal?

Why would a designer want to invert logical signals? I see inverted schmitt triggers a lot in logic circuits

Example is:
You have to invert the logic state when to light an LED , since the pull up resistor is tied to +5 volts right?

When you have to invert the logic state or signal mostly?

When I'm probing around on a logic circuit, I don't understand why a designer would want to invert the logic state or logic signal or Trigger signal or Clock signal
 

MrAl

Well-Known Member
Most Helpful Member
Hello again,


There are a lot of reasons to invert a clock signal, one is to create a two phase clock signal from a signal phase clock signal.

There are a lot of reasons to use an inverter. We might have a signal that goes high, but our next stage (that meets other requirements) needs a signal that goes low instead.

The designer might use an inverting Schmitt Trigger for the following reasons:
1. The design called for an inverted signal.
2. The designer needed a non inverting Schmitt Trigger, but didnt want to have to use a different package when there were sections left over from an existing package.
3. The company the designer works for does not want to have to stock two types of Schmitt Trigger packages (inverting and non inverting) but only one, and the inverting type is more versatile so they only want to have to stock that type.

For an example of negative logic, say we have a circuit that uses op amps to sense under voltage, over voltage, and over current. And say that these op amp sections put out a low signal when true (ie true here means we have under voltage, over voltage, or over current). So here true means low.
Now say we want to turn on a buzzer when either of these conditions occur. We need a gate that can detect ANY of three inputs going low, because we want the buzzer to go off when either of those conditions occur, any one of them. We know that an OR gate can detect either of the inputs going high, but we need to detect either input going low. So we use an AND gate. If any of the inputs of the AND gate are low, we get a low output, and if that low output is what we need to drive the buzzer then that's all we need, but if we need a high to get the buzzer to turn on, then we need a NAND gate. Since we have three inputs, we need a three input NAND gate. This way when either of the three inputs goes low we get a high output and that turns the buzzer on.
The important thing to note here is that although we are using a NAND gate (which is just an AND gate with inverted output) we are really using it as a negative logic NOR gate because EITHER of three inputs going low can make the output go high. This might be a little confusing, so lets look at the truth table for a two input AND gate...

The inputs are a and b, and the output is c:
a b c
00 0
01 0
10 0
11 1

Look carefully at the two inputs for each output. We call this gate an AND gate because in the last row we see that when BOTH inputs are HIGH that's the only condition that can cause the output to go high. So here we look at that alone, and that is positive logic. We looked only at what it takes to get a high on the output.
But now lets look at what it takes to get a low on the output. We see that there are three cases that make a low appear on the output. We note that in each case the difference between those three cases and the last case (both 1's) is that each of those three has at least one zero input. So we can generalize that observation and state that when EITHER input is zero we get a low on the output.

So you see we described this gate two different ways:
1. A high on both inputs creates a high on the output, or
2. A low on either input creates a low on the output.

They both mean the same thing because of the limitations of the signals available to digital logic, only 1's or 0's are acceptable. There are numerous other simplifications that come about because of the limitations of the available signal levels.
 
Thanks for you info.

to invert a clock signal, one is to create a two phase clock signal from a signal phase clock signal.
Yes, I have seen this, one clock signal is 180 degrees out of phase with the other one.

Any reason why they want the clock signal to be 180 degrees or have a 2 phase clock signal?


So inverting the logic state, turns a Positive logic truth table into a Negative truth table?

So A sine waveform has no slew rate?

They use Non-Inverting Schmitt triggers to convert a sine wave into a square waveform.

What's the difference between using an op amp to convert a sinewave into a square waveform or using a non-inverting schmitt trigger?

I have seen circuit that use either op amp or non inverting schmitt trigger to convert a sinewave into a square waveform but what is the difference between using an op amp or using a non-inverting schmitt trigger?
 
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