What do you mean how a NOR gate is functioned like a negative logic NAND gate, how so ? and why did the designer do this? Instead of using a NAND gate, because he used a NOR gate, why didn't the designer just use a NAND gate?
Hello again,
The decision to use an AND or OR or NAND or NOR depends on the logic signals that are already there before you decide, and what kind of output your gate needs to produce.
Im sure you've read about logic "True" and "False". True can be a high '1' or a low '0' and then False is the opposite. And you can have a true as a 1 in some locations in the circuit and true as a 0 in other locations. It all depends on what is the simplest solution when you go to design it.
In this circuit the designer had three signals that he wanted to check, those are the input signals to the NOR gate. It's drawn like a NOR gate because that's probably the kind of gate that it is advertised as being. When you go to buy one, you look for a "three input NOR gate". But the advertised name always follows the "positive logic" convention, in that it's name refers to what it would be called if it were used as a positive logic gate.
Using this gate as a positive logic gate, we would say that any single input that goes to a high state would cause the output to go low. So if we needed that kind of function, we would use this gate. Any input that goes high gives us our desired low output.
But what if we wanted a high output instead? Then we would use an OR gate. Any of the three inputs going high then causes a high output.
But wgat if we wanted to detect all three going high at the same time and provide a low output? Then we would use a NAND gate because then we would only get a low output when ALL THREE inputs went high. Otherwise we'd get a low output. So we'd be detecting all three simultaneously going high, not just one as with the other gates so far.
But that's not the end of the story either. What if we wanted to detect all three inputs going LOW instead of HIGH as before, and provide a HIGH output when this happens? Then we would need to use a NOR gate. With this kind of gate, the output only goes high when ALL THREE inputs are LOW, not high. So now we are looking for all LOW's on the inputs not highs. So we can say that the gate is a logical AND gate for the low signals, because input 1 AND input 2 AND input 3 all have to be LOW before we get our required output of a HIGH, and that output sets the following flip flop. That's the action we need, so we can call it a negative logic NAND gate. It's only drawn as a NOR gate because that's the way it is advertised and cataloged, but you can use it as a positive logic NOR gate or a negative logic NAND gate.
As far as measuring the signals, you can use a meter for static signals that do not change very fast. But when you need to see fast changing signals you need to use a scope. The inputs to that NOR gate above may require using a scope to see properly.
There are also test equipment known as Logic Probes. These devices have various functionality depending on how expensive they are. Some of the simpler ones detect a high and low with an LED or two, and some detect a Clock signal but dont show the wave shape.
It appears that if that section is working right the LED will light when you loose all three input phases. You can try testing for that if possible. To check the actual RC network you'd have to use a scope or pull one lead of each device (being careful not to wreck the component) and check the resistor with an ohm meter and the cap with a cap meter. Alternately buy those two parts, check them, then replace them on the board regardless if you suspect them.