Synching Quartz Master clock to DCF77/MSF

[ericgibbs]

hi,
Have read all the documentation on the eBay link.

Can you check how often the pulse train of 100mSec pulses, has the 200mSec pulse, is it on the minute.???

What does the leaflet that is supplied with module say.?

 

[oliverb]

Sorry not quite sure what you mean?

But in reading the leaflet I see there are 59 pulses not 58 with a 1 sec gap (max 1.8). I will need to change the logic from IC1 so IC2 triggers at 59.

 

[dougy83]

hi,
Have read all the documentation on the eBay link.

Can you check how often the pulse train of 100mSec pulses, has the 200mSec pulse, is it on the minute.???

What does the leaflet that is supplied with module say.?

I think the pulse train contains an encoded signal. Each 100ms pulse is a binary '0', and each 200ms pulse is a '1'. The current time and date is encoded in 59 bits (some are reserved), and the 60th bit is omitted; this is used as a frame sync. The first bit of each frame is always a '0' i.e. 100ms.

The fact that each bit is transmitted in a second allows for the signal to be used in the manner that Brett intends - as a 1Hz sync.

I've drawn up a quick schematic of how I would make it using your parts. The 4024 counts to 58 (actually the 59th second - the first second of a frame resets the 4024) and gates the output AND. The DCF signal is fed into a break/missing-pulse detector (top left of cct), which outputs a pulse when the first pulse of a frame is detected; pulse width determined by R1, C1.

At the end of this pulse (which is used to realign the master clock 'seconds'), the 4024 is reset. The 4024 is also reset if it goes past 58.

I haven't simulated the circuit, but it looks ok to me (for now).

EDIT: I should also say that the OR gate (bottom left) can be made using the remaining 3 inverters and an AND gate to save on the number of ICs required.

 

[ericgibbs]

Sorry not quite sure what you mean?

But in reading the leaflet I see there are 59 pulses not 58 with a 1 sec gap (max 1.8). I will need to change the logic from IC1 so IC2 triggers at 59.

hi,
The waveform shown on the eBay links shows a pattern of a 100mSec high and
1 second later a 200mSec high.???

From that simple diagram I cannot be sure if the 200mSec represents the '60' sec interval.

Its nothing like the actual 2sec high mentioned in the DCF documentation.

 

[oliverb]

Hi dougy83
First of all thanks for taking the time to draw out this circuit.

The first thing I noticed after working through yours was a basic error in mine. I needed an inverter between C1 & IC3a as I think both our C1s and go to 0v when there is > 1 sec without a pulse.
Thats the trouble with going years between doing any electronics I end up on a very steep learning curve.

You use the 1st pulse in the frame after the long break to create the min pulse. This is much better than my design as it means the dual flip flops are not needed.

I like the diodes on the 4024 OPs. I presume if extra error pulses were received taking the 4024 count over 58 it will reset itself at 58?

When the 4024 count hits 58 and it resets itself via U2b and U4a is there a delay so U1b stays high until the long break and 1st pulse are detected?

Thanks again Brett.

 

[oliverb]

hi,
The waveform shown on the eBay links shows a pattern of a 100mSec high and
1 second later a 200mSec high.???

From that simple diagram I cannot be sure if the 200mSec represents the '60' sec interval.

Its nothing like the actual 2sec high mentioned in the DCF documentation.

The "edit" position of the 100mS and 200mS pulses will vary in the frame depending on the BCD time code but they will always be 1 sec apart with a 1sec gap after the 59th sec to indicate a new frame will start on the next pulse.

 

[dougy83]

ericsgibbs,

Have a look at the diagram Brett attached above: the one that looks like a clock face. This represents the DCF data transmitted in a 1 minute frame period. Each bit is transmitted in a second: '0' is a 100ms pulse, '1' is a 200ms pulse. The 60th bit is a no-pulse to represent the frame end/start.

Your question about 200ms turning up on the minute; the answer is no. The first 14 or so bits are zeros, i.e. 100ms pulses. After that however, there may be 200ms pulses, depending on what the time is (which is sent in BCD).

 

[ericgibbs]

ericsgibbs,

Have a look at the diagram Brett attached above: the one that looks like a clock face. This represents the DCF data transmitted in a 1 minute frame period. Each bit is transmitted in a second: '0' is a 100ms pulse, '1' is a 200ms pulse. The 60th bit is a no-pulse to represent the frame end/start.

Your question about 200ms turning up on the minute; the answer is no. The first 14 or so bits are zeros, i.e. 100ms pulses. After that however, there may be 200ms pulses, depending on what the time is (which is sent in BCD).

hi,
I see and understand clearly the DCF format, what I am not sure about is the output from the module that Brett has bought from eBay.

If you look at the eBay link it just shows 100mS and 1sec later 200mS.

I would like to see what other information is on the documentation that was supplied with the module, thats all I keep asking for.

 

[oliverb]

Hi the output format is as the DSF77 but pulse amplitude .7v below VDD.
There is no other info with the module bar the pin outs and info on the DCF77 code.

The module works from 1.2 to 5.5v.

edit The diagram with the module just shows a random sample from a frame of data.

Brett.

 

[wombweller]

Hi All

Been watching this thread with interest!! a topic of which lots of us have considered implementing into Our clock projects.

Brett well done thus far good to see that your advancing forwards with it all,Your getting some following with your master clock!!

Not sure why you went for the DCF.time signal other than cost!! but please explain to a novice does this also mean you can't in the future 'if required' take advantage of the BST. info with the MSF. version?

Looking at the ebay link I'm thinking that the supplier as not fully illustrated the the bits of a complete minute and one would read from the info on the wave form that it only consists of the 100ms and 200ms pulses each 1000ms for the entire 1 min although we know this is not so for the DCF. signal.

Trouble here is when someone supplies something already built as in the ebay DCF77 we have to understand just how these work also.



Nice work!!

Wombweller!!

 

[oliverb]

Hi Wombweller.

I don't think it matters weather you go for MSF or DCF77 in the UK especially down South. Manufacturers supply both in clocks and watches for UK use. When I purchased my DCF77 there was a masive cost differance but I have now found a MSF module for £25 inc postage.


As far as using a MSF module instead of a DCF77 there should not be too much of a problem. I think the MSF uses a 500ms pulse to indicate the start of the frame in the 1st second rather than a blank in the 59th. I'll have to check to make sure.

This should off the top of my head mean only a few circuit changes to get it going.

 

[dougy83]

hi,
I see and understand clearly the DCF format, what I am not sure about is the output from the module that Brett has bought from eBay.

If you look at the eBay link it just shows 100mS and 1sec later 200mS.

I would like to see what other information is on the documentation that was supplied with the module, thats all I keep asking for.

The module output is the demodulated dcf signal, inverted.

 

[Mr RB]

Hi Wombweller.

I don't think it matters weather you go for MSF or DCF77 in the UK especially down South. Manufacturers supply both in clocks and watches for UK use. When I purchased my DCF77 there was a masive cost differance but I have now found a MSF module for £25 inc postage. ...

Youch! I was annoyed having to pay $39 USD for a GPS module. (edit) Sorry just realised your price included postage.

Re my earlier post about the possibility of synching to a glitch, it still exists using the circuits suggested above. Imagine if you get 57 good pulses then a nasty glitch with a couple of noise pulses followed by a signal dropout. The circuit would interpret this as 59 good pulses followed by the pause, so your entire system would sync that minute 2 seconds early! Ouch.

Since you seem to have some schmidt inverters free, why not whack a big RC time constant on the front end then an inverter to schmidt it back to digital, and one to invert the signal again. This adresses the weakness of the circuit to be triggered by glitches, provided you make the time constant of the RC circuit close to max. This will save you from both positive and negative glitches unless of course they are very long in length. It may also be worth putting a small RC right on the 4042 counters clock input pin, in case of psu glitches.

 

[dougy83]

Fair enough. To free up the inverters (used for the OR gate), replace the OR gate with 2 diodes and a resistor.

 

[oliverb]

Since you seem to have some schmidt inverters free, why not whack a big RC time constant on the front end then an inverter to schmidt it back to digital, and one to invert the signal again. This adresses the weakness of the circuit to be triggered by glitches, provided you make the time constant of the RC circuit close to max. This will save you from both positive and negative glitches unless of course they are very long in length. It may also be worth putting a small RC right on the 4042 counters clock input pin, in case of psu glitches.

Hi I can see what you mean about problems with glitches but I'm not sure if I understand your solution.

Are you saying use RC to filter or error check any very slow or very fast pulses ie less than 1ms or over 1.8 secs?

Can you show the solution on a diagram, an extra IC is not too much of a problem I was expecting a far more complicated solution anyway.

 

[Mr RB]

Sorry no diagram but it's easy enough. Run the incoming signal through a resistor with a cap to ground. Make the RC time constant large so it JUST reaches full 5v voltage at the end of a 100mS high pulse which is your shortest incoming pulse. Then just put it through 2 schmidt inverters (in series) to clean it back up to digital again with the correct phase.

The big RC low-pass filter on the front end will save the circuit from triggering on any short glitches that might occur, either 1 glitches or 0 glitches will both be removed provided they are short ones. ie a HI pulse (or following LO pulse) must be at least 100mS long (actually about 60mS?) to trigger the schmidt inverter and cause a proper digital pulse.

The only down side is the cost of R and C and 2 inverters, and a typical lag of 60mS. Personally I would prefer a 60mS lag every minute than risk glitches which definitely can cause a failure to sync or a 1 second sync error.

 

[dougy83]

Mr RB was suggesting something like the attached cct. (I know his explanation was good, but still it never hurts to have a concrete dwg)

You may want to twiddle the component values, of course.

 

[oliverb]

Thanks again MrRB and thanks for the diagram dougy83.

An extra chip or 2 is not a problem and 60ms lag is nothing compared to a clock to a clock that slowly drifts out.

Comparing my wife's radio alarm clock to mine (diff makes) they are a fraction of a second out of sync with each other.

I think I will try and prototype the circuit later this week, will let you know how it goes.

 

[dougy83]

Just thinking... if you're worried about short glitches, then perhaps we should get rid of long ones too. The spare inverter can be used to reset the counter if the input signal remains for too long either high or low.

Have a look at the attached cct.

I didn't calculate the time constants so they may need tweaking, but they should be in the ballpark.

 

[oliverb]

Thanks again dougy83.

I have now built the circuit on vero board and have drawn out your circuit in live wire and uploaded a copy.

I have changed the values of VR1 and C1 (on my diagram) to 50k and 100µF as IC2a was being held low.

I am having a few problems with the circuit and think I need to tweek a few components.

The circuit works fine if I disconnect R7 (R4 on dougy83's diagram) where it goes to IC2d and connect R7 to +ve.

The inverter IC2d with R7 disconnected is perm high on it's output.

Can anyone explain how the 2 RC combinations C7&R9 (R12&C8)and R8&C8 (R11&C7) work in this circuit so I can work out what components require changing?

I think R8 & C8 will charge for a pulse longer than a second so that will be 2 seconds as IC2a only goes high after a 1 sec pulse?

Does C7 only discharge on very long pulses over 4 seconds so normally IC2d OP would be low?

I suppose I could disconnect each RC combination in turn where it goes into IC2d and see which one is the culprit. Then adjust values to make it work.

Thanks in advance. Brett.