Continue to Site

Welcome to our site!

Electro Tech is an online community (with over 170,000 members) who enjoy talking about and building electronic circuits, projects and gadgets. To participate you need to register. Registration is free. Click here to register now.

  • Welcome to our site! Electro Tech is an online community (with over 170,000 members) who enjoy talking about and building electronic circuits, projects and gadgets. To participate you need to register. Registration is free. Click here to register now.

SPI communication.

Status
Not open for further replies.

alphacat

New Member
I have questions please about the CPOL and CPHA that need to be set at the master and slave devices.


1.
For CPHA = 0, data is read on clock's rising edge, but when is the data sent? half-cycle before the clock's rising edge?

2.
Must the master and slave devices must be configured to have the same CPOL and CPHA values?

If so, what happens if you have one Master (Uc) and 2 Slaves, where one Slave is configured to have CPHA=1, and one slave is configured to have CPHA=0?
(and the slave doesnt give you the option to set their CPHA to a desired value).

3.
Must the data on the MOSI and MISO lines stay stable for half a cycle before the "reading transition", and also for half a cycle after the "reading transition".
(For CPHA=0, the "reading transition" is the rising transition).

Thank you very much.
 
Last edited:
What's a 'cycle'? You have to read the datasheet for whatever you are communicating with, but generally dedicated slave devices will read data on the input line within nano seconds of the clock signal.
 
There are a ton of devices that you can't change settings for like sd spi... You have to code your uc to work with the different types. Spi is simple... When you've done your reading :D
 
Hey,
I already read the entire Wiki article + the Microchip article, and now I read the pages your linked me to (thanks for that).

1.
I see also in pages 15,17, and also on Wiki, that the data on the MISO/MOSI line stays stable half a (clock's) cycle before the sampling, and half a cycle after the sampling.
Is it a must?

2.
Must the master and slave devices must be configured to have the same CPOL and CPHA values?

If so, what happens if you have one Master (Uc) and 2 Slaves, where one Slave is configured to have CPHA=1, and one slave is configured to have CPHA=0?
(and the slave doesnt give you the option to set their CPHA to a desired value).
 
As i said before. There are many slaves with fixed communication methods as SD (SPI) is. This is something you have to setup in your MCU. The master (MCU) is supposed to adjust itself for your device (SLAVE).

If they both have different values i assume a mix up of data is the conclusion. You wont get bits right. You might skip some or might not even be able to communicate and may even require a reset to both devices.

Thats MID sample your talking about i think... There are 2 types MID and END. If its mid you should set or clear the clock depending on the idle state and once you set the clock read the data then set or clear the clock to tell the device to load a new value.

Whats so hard?
 
As i said before. There are many slaves with fixed communication methods as SD (SPI) is. This is something you have to setup in your MCU. The master (MCU) is supposed to adjust itself for your device (SLAVE).

If they both have different values i assume a mix up of data is the conclusion. You wont get bits right. You might skip some or might not even be able to communicate and may even require a reset to both devices.
Thank you.

Thats MID sample your talking about i think... There are 2 types MID and END. If its mid you should set or clear the clock depending on the idle state and once you set the clock read the data then set or clear the clock to tell the device to load a new value.
The master device can be configured to either sample at the MID or the the END.
But, the slave device must be configured to sample at the MID.
That is accroding to Microchip presentation (do you know why the slave must sample at MID?).

What i'm actually asking is, When one samples data (Master or Slave), must the data stay stable for half a cycle before one samples it?
 
Last edited:
If you're using the built in SPI module, then you need not concern yourself with sampling the data at all. I recently used an SPI module for the first time, and I set mine up for mid sampling. There was no real science behind this, it just seemed the most sensible to me and I thought I'd give it a try. It worked. Sometimes, even when you've read all the documentation you can find, there's just no subsitute for trying it.

But as I was saying, if you're using the SPI module then you don't concern yourself with when to sample the data. You just write to the SSPBUF to transmit and the PIC does the rest, based on how you've set it up. Be aware that even if you're not intending to receive any information, you must still read the SSPBUF before you send another data byte - otherwise you'll get write-collisions and it won't work.

Sorry I can't be a technical authority on this, I'm quite new to it myself.

Brian
 
Oh, and with regard to whether the clock line should be normally low or normally high... yeah that depends on your application and it will matter. You'll need to read the documentation for the device you're communicating with. If it's not clear, then... well it's a simple bit in the SSP register so not too much trouble to try it both ways?

Brian
 
Isnt there a requirement with shift registers that the data will be stable a cetrain time before they sample the data?
 
I'm not able to relate what you're saying to a problem you're experiencing with the SPI Module on the PIC?

You don't concern yourself with sampling the data when you use the built in SSP Module. The SSP Module samples the data for you and stores the result in SSPBUF. All you need to concern yourself with is reading the SSPBUF register when it is full.

Brian
 
ok to end this thing.... yes its important on sample times. You have to let the data settle to ensure a correct sample from the device.

If you use the SPI hardware it does it for you correctly without you having to worry...

if you use SPI BitBang then you have to refer to the data sheet to know how long to wait before sampling data.
 
@ThermalRunAway
I dont want to look at the SSP module as a black box, but would like to understand how it works.

@AtomSoft
Thank you very much :)
You're right, i looked at some slave's datasheet and it indeed showed there the minumum time that the data should be stable before its sampled.
Thats what i wanted to know.
Greetings!
 
Last edited:
heh you dont have to read it all. Its not a book heh its a manual for reference. You just jump to the parts you need to lookup :D

They are very usefull heh
 
@ThermalRunAway
I dont want to look at the SSP module as a black box, but would like to understand how it works.

Ah okay, then we misunderstand each other. I thought you were asking with reference to a problem you were experiencing with the SSP module, rather than academic interest.

Brian
 
Its not really an academic interest.

If you go to an interview and are asked about what you did at your previous job for example, i dont want to tell them that i just wrote data into the buffer register and read the buffer once the TX_FLAG was set.

Don't you agree with me on that?
 
Last edited:
heh i never had a job with electronics but never thought there would be great detail in a interview before heh

I wish i could find a job doing this stuff then i would enjoy work heh
 
Status
Not open for further replies.

Latest threads

New Articles From Microcontroller Tips

Back
Top