CMOS logic gates, in the way they are designed, consume almost no current when the gates aren't changing, because the basic CMOS gate circuit is made of a pair of complementary MOSFETs, such that when one is on, the other is always off. But, leave a gate input floating, and it's possible for both MOSFETs to partially turn on at the same time, if the gates are in the FET's linear regions, causing a current flow through them (from Vdd to ground). Also, a small amount of current is drawn when the gate switches from high to low or vice versa, due to the instant of time that both MOSFETs are on, and to overcome gate capacitance. Leaving an input floating can lead to both of these issues (both high-side and low-side FETs on, or rapidly switching states).