Open drain output

[alphacat]

Hey,

I wanted to ask you guys please:

1. I read in Wiki that sometimes ICs provide a weak internal pull-up resistor to connect the drain to Vdd in order to reduce power usage by keeping input signals from floating.
How exactly does it reduce power usage?
(floating => high impedance => minumum current => minimun power usage).

2. It was also said that external strong pull-up resistor are used to minimize noise.
How does a strong pull-up reduce noise, compared with a weak one?

Thanks in advance.

 

[Speakerguy]

1. I read in Wiki that sometimes ICs provide a weak internal pull-up resistor to connect the drain to Vdd in order to reduce power usage by keeping input signals from floating.

Excellent question. Floating inputs are high impedance, and thus are susceptible to noise. Noise can then cause the state of the pin to change, and it can do so quite rapidly. If the pin is connected to any internal logic, it will also change state. I work with ultra low power electronics for a living, and it is very very important that we don't have any floating inputs anywhere in a system. Most devices have pull ups or "bus keepers" which are two series inverter gates that feed back to the pin to keep it in a constant state, but which only have limited current capability (so that an actual applied signal is strong enough to overcome them).

t was also said that external strong pull-up resistor are used to minimize noise.

The stronger the pull-up, the higher the noise has to be to get the pin to toggle. A weak pull-up might draw 100uA, a strong one might draw 1mA. For noise induced on the pin by a stray RF field, it is much harder to overcome the constant 1mA current on the pin than the 100uA one. The RF field has to be much stronger.

 

[alphacat]

Excellent question. Floating inputs are high impedance, and thus are susceptible to noise. Noise can then cause the state of the pin to change, and it can do so quite rapidly.

Noise where? at the drain's terminal or at the Gate's terminal?
Noise at the Gate terminal will still affect the output, no matter if its floating or not, won't it?

If the pin is connected to any internal logic, it will also change state. I work with ultra low power electronics for a living, and it is very very important that we don't have any floating inputs anywhere in a system. Most devices have pull ups or "bus keepers" which are two series inverter gates that feed back to the pin to keep it in a constant state, but which only have limited current capability (so that an actual applied signal is strong enough to overcome them).

Thank you.
I'm not sure though, how does it reduce the power usage in the circuit?
(By the way, there are cases where you would want to have floting pins in the system, for example when a master device is to communicate with several slaves).

The stronger the pull-up, the higher the noise has to be to get the pin to toggle. A weak pull-up might draw 100uA, a strong one might draw 1mA. For noise induced on the pin by a stray RF field, it is much harder to overcome the constant 1mA current on the pin than the 100uA one. The RF field has to be much stronger.

Thank you again, that indeed answers my question about reducing noise.

 

[kpatz]

Noise where? at the drain's terminal or at the Gate's terminal?
Noise at the Gate terminal will still affect the output, no matter if its floating or not, won't it?

The gate is very high impedance, meaning very little current is needed to change its state. When floating, noise/RFI/EMF can cause the floating input to toggle randomly, causing various issues. When you use a pullup or pulldown, the gate is tied to a fixed voltage so it's at a high or low. It will take a lot more noise energy to overcome the pullup/down voltage than on a floating pin.

Thank you.
I'm not sure though, how does it reduce the power usage in the circuit?
(By the way, there are cases where you would want to have floting pins in the system, for example when a master device is to communicate with several slaves).

CMOS logic gates, in the way they are designed, consume almost no current when the gates aren't changing, because the basic CMOS gate circuit is made of a pair of complementary MOSFETs, such that when one is on, the other is always off. But, leave a gate input floating, and it's possible for both MOSFETs to partially turn on at the same time, if the gates are in the FET's linear regions, causing a current flow through them (from Vdd to ground). Also, a small amount of current is drawn when the gate switches from high to low or vice versa, due to the instant of time that both MOSFETs are on, and to overcome gate capacitance. Leaving an input floating can lead to both of these issues (both high-side and low-side FETs on, or rapidly switching states).

 

[MikeMl]

Hey,

I wanted to ask you guys please:

1. I read in Wiki that sometimes ICs provide a weak internal pull-up resistor to connect the drain to Vdd in order to reduce power usage by keeping input signals from floating.
How exactly does it reduce power usage?
(floating => high impedance => minumum current => minimun power usage).

The weak pullup is used to prevent the open drain pin from "floating" at a voltage mid way between Vdd and Gnd. Presumably, there is a CMOS input connected to the floating node, either to the same pin (if it is a bidirectional pin), or in another chip somewhere else.

If the voltage floats to a level roughly halfway, the Pchannel and the Nchannel transistors that are part of a CMOS input structure both are turned on at the same time. This causes current to flow from Vdd to ground, wasting power and heating the chip. Normally, CMOS inputs are supposed to switch through that range in a very short time. Preventing the input from floating around is why the weak pullup is there.

2. It was also said that external strong pull-up resistor are used to minimize noise.
How does a strong pull-up reduce noise, compared with a weak one?

Thanks in advance.

Imagine an open-drain output connected via a long wire to a remote CMOS input. The more current that the pull-up resistor can source, the less likely it is that the voltage on the wire will be effected by capacitive coupling to other non-related signals. i.e. this raises the "noise-immunity" of the signal wire.

 

[alphacat]

The gate is very high impedance, meaning very little current is needed to change its state. When floating, noise/RFI/EMF can cause the floating input to toggle randomly, causing various issues. When you use a pullup or pulldown, the gate is tied to a fixed voltage so it's at a high or low. It will take a lot more noise energy to overcome the pullup/down voltage than on a floating pin.

I thought that the open-drain output is the terminal that you connect the strong pull-up resistor to in order to reduce noise affect.
So you also connect a pull-up resistor to the Gate terminal?

CMOS logic gates, in the way they are designed, consume almost no current when the gates aren't changing, because the basic CMOS gate circuit is made of a pair of complementary MOSFETs, such that when one is on, the other is always off. But, leave a gate input floating, and it's possible for both MOSFETs to partially turn on at the same time, if the gates are in the FET's linear regions, causing a current flow through them (from Vdd to ground). Also, a small amount of current is drawn when the gate switches from high to low or vice versa, due to the instant of time that both MOSFETs are on, and to overcome gate capacitance. Leaving an input floating can lead to both of these issues (both high-side and low-side FETs on, or rapidly switching states).

I still dont get how its got to do with connecting weak pull-ups to the open-drain output in order to reduce power usage.

 

[alphacat]

The weak pullup is used to prevent the open drain pin from "floating" at a voltage mid way between Vdd and Gnd. Presumably, there is a CMOS input connected to the floating node, either to the same pin (if it is a bidirectional pin), or in another chip somewhere else.

If the voltage floats to a level roughly halfway, the Pchannel and the Nchannel transistors that are part of a CMOS input structure both are turned on at the same time. This causes current to flow from Vdd to ground, wasting power and heating the chip. Normally, CMOS inputs are supposed to switch through that range in a very short time. Preventing the input from floating around is why the weak pullup is there.



Imagine an open-drain output connected via a long wire to a remote CMOS input. The more current that the pull-up resistor can source, the less likely it is that the voltage on the wire will be effected by capacitive coupling to other non-related signals. i.e. this raises the "noise-immunity" of the signal wire.

Got you!

Thanks a lot !

 

[alphacat]

The more current that the pull-up resistor can source, the less likely it is that the voltage on the wire will be effected by capacitive coupling to other non-related signals.

By the way, dont you mean that its less likely that the current throught the wire wil be effect by inductive coupling ?

After all, the voltage level remains the same for both weak and strong pull-up, but the current changes.

 

[MikeMl]

By the way, dont you mean that its less likely that the current throught the wire wil be effect by inductive coupling ?

After all, the voltage level remains the same for both weak and strong pull-up, but the current changes.

There are two ways that "noise" can be induced into the wire, capacitive coupling from a parallel wire that is being switched, or by magnetic induction into the loop that the wire is part of. Forcing the wire to a voltage with a lowΩ resistor vs a highΩ provides improved noise immunity for both cases...

 

[alphacat]

Yes, I understand now.

Thanks a lot!

 

[alphacat]

Hey,

Am I correctly describing the problem that capacitive coupling might cause?

* The D-S channel of M1 is open (high impedance).

 

[alphacat]

Could anyone help me out understanding it please?

 

[kpatz]

It would be like this:

The floating gate would pick up noise from the high-speed line, causing the FET to switch/amplify the noise.

 

[alphacat]

Thank you.

So how does the Pull-up at the Drain terminal, help preventing the noise at the Gate terminal from closing the D-S channel?

 

[MikeMl]

Hey,

Am I correctly describing the problem that capacitive coupling might cause?

* The D-S channel of M1 is open (high impedance).

You have the source of the capacitive noise coupling correctly depicted, but the equation is a bit flaky. Instead of the VCC in the voltage divider equation, the numerator should have the amplitude of the signal being coupled from the parallel signal line.

Rarely, does crosstalk perturb a CMOS input connected to a wire when it is fully pulled-up or fully-pulled down. Rather, imagine what happens if the parallel signal line is switching while the weakly pulled-up line is transitioning from low to high. Because there might be tens of pF of capacitance on the wire, the weak pullup creates a long time constant as that capacitance charges though the pullup resistor. This means that the CMOS input remains in the region where it is very sensitive to small capacitively coupled spikes for a relatively long time. Contrast that to the wire being driven by a true push-pull CMOS or TTL driver, where the wire capacitance can be charged/discharged in equally short times.

 

[alphacat]

Thanks alot Mike.

Am I right about the following analysis?

If I am, then it means you need a strong pull-up just to have a low value of R1 / (R1 +Zc)

 

[alphacat]

Anyone please?