Continue to Site

Welcome to our site!

Electro Tech is an online community (with over 170,000 members) who enjoy talking about and building electronic circuits, projects and gadgets. To participate you need to register. Registration is free. Click here to register now.

  • Welcome to our site! Electro Tech is an online community (with over 170,000 members) who enjoy talking about and building electronic circuits, projects and gadgets. To participate you need to register. Registration is free. Click here to register now.

Misc Electronic Questions

Status
Not open for further replies.
oh, so its the base resistor that current limits down to lower current and the diode clamps the voltage at -0.7

If the Current is not limited or low, the diode clamp will melt? and get hot?
 
The datasheet for the diode shows its absolute maximum allowed current when it is very hot. The datasheet also shows its maximum and typical forward voltage drop at various currents and at various temperatures.
 
CMOS gates need a pull down resistor because the input capacitances needs to discharge to the pull down resistor?

Using a CMOS gate without a pull down resistor you won't get an output signal when you remove the input signal?
 
When using a protection diode does it make a logic high and low states have sharp edges and not have hysersis?
No. A protection diode prevents damage to the reverse-biased emitter-base junction when signals try to produce more than -5V.

High frequency and high voltage gain logic circuits and transistors produce sharp edges without hysteresis.
Hysteresis produces sharp edges because it is positive feedback.
 
CMOS gates need a pull down resistor because the input capacitances needs to discharge to the pull down resistor?
Cmos gates do not need a pull down resistor when they are driven from a logic IC.
The driving logic signal provides the input of a gate with a logic 0 or a logic 1. The input capacitance of a logic gate is extremely small and does not need to be discharged. But a Cmos logic input "floats" when it is not connected to a logic signal so it could be high, low or oscillating.

Using a CMOS gate without a pull down resistor you won't get an output signal when you remove the input signal?
The input to a logic gate is usually NEVER removed. Then a resistor is not needed.
 
My manager says you have to have pull down resistors on CMOS gates because the inputs and outputs are floating, high impendance, and the FETS inside the CMOS gate has capacitance that needs to be discharged, the pull down resistor discharges the FET's capacitance

Is this true or not?
 
The 3rd , 7th, 13th harmonics is the most important because when you use filters to level out the 3rd, 7th, 13th harmonics is turns a square waveform into a sine waveform

A power factor of 0.7 is what phase shift degree?
A power factor of 1 is what phase shift degree?

A power factor is a phase shift/degree

Harmonics are caused by the power supply filter caps voltage to current phase shift ,and switching, switching frequency?

Linear load has Zero power factor

A Capacitance load has a power factor of 0.7 or 1 or other?

A Inductive load has a power factor of 0.7, 1 or other?

A Capacitance load has which harmonics?
A Inductive load has which harmonics?

Non Linear loads has harmonics , why?

A Non Linear load sets the power factor?
 
pull downs: Need to see an example. CMOS outputs don't float unless they are open drain.

Your understanding of power and power factor is all messed up. Let's do some of the simple things.

Power P is normally V * I, but if both waveforms are sinusoidal then P=V*I* cos(θ)
cos(θ) is the power factor. Cos(zero) is equal to 1.

the OP said:
Linear load has Zero power factor

No, your confusing phase angle with power factor.

the OP said:
A power factor is a phase shift/degree

No.

the OP said:
A power factor of 1 is what phase shift degree?
Zero If and Only if the current and voltage waveforms are identical (usually sinusoidal)

I always have to look up the definitions of leading and lagging because I don't deal with this stuff every day. Buildings can have large capacitor banks that are automatically switched to raise the power factor closer to 1.

Harmonics: I need to think about how to answer

many times, PF is expressed also with leading and lagging. Look here first: https://en.wikipedia.org/wiki/Power_factor
 
To help me remember leading and lagging, I like the ELI, the ICE man, E lead I for inductance, I leads E for capacitance.
 
We have to start somewhere, so it might as well be here: https://en.wikipedia.org/wiki/Electric_power

Real power (Watts)
Apparent power (VA)
Reactive power (VAR)

What this really means is the utility gets very upset at industrial customers that have very bad power factors. The bad power factors are usually caused by inductances from large motors.

So, why do they get upset? Because their transmission lines overheat because the currents are much higher than they would be for a purely resistive load. You really want the reactive power to be zero. You want all the power produced to be turned into energy and NOT returned to the source as essentially a circulating current.

PF =1 means that the cos(θ) = 0 for sinusoidal voltages and sinusoidal currents. It means that there is no phase difference between the voltage and currents.

You have to understand DC power first in terms that P= V*I and that a positive sign is power DISSIPATED. You also have to know when the sign is understood. e.g. a 16 MW power plant is really a -16 MW power plant and the homes dissipate the power. i.e. 16 mW = homes * power per home

Then you step up a bit and learn that if a load is resistive and the voltage is AC, the same P=V*I relationship holds and that the RMS value of the AC is the equivalent DC voltage to the same resistive load.

Then you move to voltages and currents are both sinusoidal and now P = V * I cos (θ)

And hopefully when you add a complex load like a VFD, a PC switchmode power supply, an electronic ballast, or even a non-electronic ballast the current waveforms are anything but sinusoidal. The simple relationships don't apply any more and it's likely that the devices will employ some sort of power factor correction. Power factor correction basically means the current drawn from the mains needs to be an average current.

See here: https://www.electro-tech-online.com/custompdfs/2013/04/pfc_switchmode_powersupplies.pdf
 
My manager says you have to have pull down resistors on CMOS gates because the inputs and outputs are floating, high impendance, and the FETS inside the CMOS gate has capacitance that needs to be discharged, the pull down resistor discharges the FET's capacitance
Is this true or not?
Not true.
Cmos logic circuits have many gates, counters and other logic devices all connected together with NO pull down resistors. The input capacitance is extremely low and does not need to be discharged.
If a Cmos input is not being used for logic then it does not need a resistor, it is simply connected directly to 0V or to the positive supply.
 

Attachments

  • Cmos input capacitance.png
    Cmos input capacitance.png
    12.4 KB · Views: 212
The 3rd , 7th, 13th harmonics is the most important because when you use filters to level out the 3rd, 7th, 13th harmonics is turns a square waveform into a sine waveform
Not true because the 5th, 9th, 11th and higher odd harmonics are still there. Also even harmonics must also be filtered out.
A pure sinewave has no harmonics.
 
So Does TTL need pull down resistors so the input capacitance needs to discharge?

PF =1 means that the cos(θ) = 0 for sinusoidal voltages and sinusoidal currents. It means that there is no phase difference between the voltage and currents.

PF= 0.7, is the voltage and current sinusoidal and no phase difference?

Why does a circuit board create harmonics on the AC unity when hooked up? what is causing these harmonics?

Does having non- linear loads cause harmonics and changes the PF factor?
 
Does TTL need pull down resistors so the input capacitance needs to discharge?
Why do you ask about input capacitance? It is so low that the datasheet does not spec it. It might be only a few pF and does not need to be discharged.

The inputs are the emitters of a turned on NPN transistor so they float high. If an input is not used and you need it to be a logic low then simply connect it to 0V, a pull down resistor is not needed.
Old fashioned, high supply current TTL needs a fairly high input-low current of 1.6mA as shown on its datasheet.
 

Attachments

  • TTL inputs.png
    TTL inputs.png
    27.8 KB · Views: 210
The harmonics problem was covered here: https://www.electro-tech-online.com/custompdfs/2013/04/pfc_switchmode_powersupplies.pdf

PF = 0.7; the voltage and current do not need to be sinusoidal. Now specify leading or lagging, ELI the ICE man. V leads I when inductive.

You can see some interesting formulas here: **broken link removed**

Note, how the inductive and capacitive reluctance can cancel each other. Also note that PF = R/Z; It also implies that R=Z when PF =1.

http://www.labsanywhere.net/circuit/lectures/lect12/lecture12.php

Other equations for power: https://www.electro-tech-online.com...ions20Useful20in20AC20Power20Calculations.pdf
 
Using Transistors as switches

Don't they have hysteresis problems? how do you not have hysteresis when using transistors as a switch?
 
Status
Not open for further replies.

Latest threads

New Articles From Microcontroller Tips

Back
Top