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# LTSpice Half bridge inverter

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#### ogeuh

##### New Member
I am trying to create a simple half bridge inverter in LTSpice. I have chosen to use a purely inductive load and I am having some problems with the circuit.
I am using a gate driver the IR2110a to drive the MOSFETS.
The problems I am having are the output voltage (Vs-Va) is not as expected. I was expecting the midpoint between the capacitors C3 and C1 (Va) to be constant at a value of Vrail/2 but it is oscillating as a sine wave which I believe may be causing this issue. Why is Va acting in this way?

Another issue (which may be linked) is the value of Vs becomes greater than Vrail at times in the circuit- due to the inductive load- is this normal or can I solve this? Am I correct that the high side mosfet cannot function correctly if Vs becomes higher than Vrail while M1 is on and the current will flow through D2 causing M1 to be ineffective?

Below is the LTSpice circuit and the output graphs, I have done it here at 100Hz pwm frequency and 1kHz and 10kHz pulse frequency

I have tried changing a number of parameters such as capacitor values, rail voltage and frequency to solve the issues with no success.
If anyone has any explanations or solutions of what I am doing incorrectly that would be much appreciated.
Any queries about the circuit or what I am asking let me know

#### Attachments

• 10kHz.png
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• 1kHz.png
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Welcome to ETO!
Why is Va acting in this way?
Because you are charging/discharging C1 and C3 via the load.
the value of Vs becomes greater than Vrail at times in the circuit- due to the inductive load- is this normal
Yes. It's the way the bootstrap arrangement works to ensure the gate voltage for the high-side FET (M1) is sufficiently above the FET source voltage to turn the FET fully on.
Incidentally, your circuit provides no dead-time between M1 switching off and M2 switching on, so shoot-through may be a problem.

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Hello!
Here is my .asc file but I am having trouble uploading the .cir file of the IR2110a gate driver to this website so it may not run.

Ok so I think I understand why Va is acting like the sine wave, is my output voltage (Vs-Va) then correct?

Am I correct that adding a resistor to the load will stop the Vs acting in a sine shape and will become change between Vrail/2 and zero only? Is this due to a smaller current in the circuit so the inductive load has a smaller effect on the charging of the capacitors?

(NB; I believe the gate driver, IR2110a, has built in dead time so shoot-through should not be an issue)

#### Attachments

• hb_pwm_lab.asc
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