LTspice AC/DC convertor

[alec_t]

Get rid of E1. Put B2 in its place, with V=delay(v(GTDR),5u). But this is only a kludge and will not give true interleaved PFC, because the 1249 oscillator frequency/pulse-width are not constant.

 

[mading2018]

the 1249 oscillator frequency/pulse-width are not constant.

I understand now. Hmm, which IC circuit does have constant frequency/PW?

I got a tip from my supervisor to use an inverter instead for the delay, so I will try with that as well.

 

[alec_t]

which IC circuit does have constant frequency/PW?

The LT1248.
I think using an inverter will mean that one half of the PFC will be fighting the other half of the PFC!

 

[eTech]

Hi

GTDR is running at about 30Khz. Period 33.2us, Pulse width about 4.3us. I believe each mosfet should alternately trigger on the leading edge of each GTDR output pulse (not on the same output pulse) which means each will operate at half of the frequency of GTDR. So if you really want this to run at 100khz , the operating frequency needs to be higher.

See image.



eT

 

[mading2018]

The LT1248.
I think using an inverter will mean that one half of the PFC will be fighting the other half of the PFC!

I tried now with LT1248. Yes, I agree that the inverter could be a bad idea. I keep the BV source with delay.

which means each will operate at half of the frequency of GTDR.

Aha, okay, thats true. I doubled that frequency in that case to 200 kHz, see images. The input of the current still have some spikes :/

 

[alec_t]

I doubled that frequency in that case to 200 kHz

Ok, but although the PFC is now 'interleaved' (after a fashion), both FETS trigger on each GTDR pulse rather than on alternate pulses as etech mentions in post #84. I don't know enough about PFC to say if that's adequate, but perhaps it's ok with your supervisor?

 

[mading2018]

I believe each mosfet should alternately trigger on the leading edge of each GTDR output pulse (not on the same output pulse)

How could I accomplish that that if I would like to try? With some kind of logic gates?

 

[mading2018]

Ok, but although the PFC is now 'interleaved' (after a fashion), both FETS trigger on each GTDR pulse rather than on alternate pulses as etech mentions in post #84. I don't know enough about PFC to say if that's adequate, but perhaps it's ok with your supervisor?

I am gonna check with him, and let you know.

 

[alec_t]

With some kind of logic gates?

Yes. A flip-flop can give you alternate pulses. In LTspice you have the srflop, That could be used in conjunction with AND gates to steer gate-drive pulses. The output voltage of logic gates can be set to, say, 10V for driving MOSFET gates.

 

[mading2018]

That could be used in conjunction with AND gates to steer gate-drive pulses.

Hmm, how can the logic control look like alec_t? Not sure where to implement 10 V. Fundamental logic gates is not my strongest subject :/ sorry about that.

--edit--
I mean the logic gates look different here in LTspice I think. I found this demo, that could help a bit.

 

[alec_t]

I found this demo, that could help a bit.

Yes. That shows how parameter Vhigh gives a 5V output (change it to 10V). LTS 'Help' describes this.

 

[ChrisP58]

Yes. A flip-flop can give you alternate pulses. In LTspice you have the srflop, That could be used in conjunction with AND gates to steer gate-drive pulses. The output voltage of logic gates can be set to, say, 10V for driving MOSFET gates.

I think that if you want each mosfet to get alternate pulses, then a D-flipflop, set up as a divide by 2 would work better. Then separately AND Q and Q-not with GTDR to feed the two mosfets.

 

[alec_t]

Chris is right. Brain phart on my part.

 

[eTech]

The ff output will also need to incorporate “deadtime”...a small duration of time (usually nanoseconds) when neither mosfet is on.

eT

 

[mading2018]

I think that if you want each mosfet to get alternate pulses, then a D-flipflop, set up as a divide by 2 would work better. Then separately AND Q and Q-not with GTDR to feed the two mosfets.

Chris, and alec_t, what do you mean divided by two? I have attached the file once more, so you can see the connection. I may have misunderstood something.

The ff output will also need to incorporate “deadtime”...a small duration of time (usually nanoseconds) when neither mosfet is on.

I think there is small deadtime in the attribute editor of the D-flipflop of 10 ns.

 

[eTech]

I think there is small deadtime in the attribute editor of the D-flipflop of 10 ns.

uh... no...it is virtually instantaneous. There is no deadtime..

 

[alec_t]

The D-flipflop does not itself provide dead-time (the interval needed between one MOSFET switching off and the other MOSFET switching on). The 10nS parameter you referred to is the response time of the flipflop.

 

[ChrisP58]

You make divide by 2 with a D-flipflop by feeding it's D input from it's own Q-not output.

Feed the GTDR to the CLK pin of the D-flipflop. Q and Q-not goes to one input of two AND gates. GTDR goes to the other input of the AND gates. The outputs of the two AND gates drives the mosfets.

No dead time is needed on the output of the flipflop, because we are ANDing it's output with the original gate pulse. (*) This will maintain the same modulated pulse width, but it's now alternately directed to the two mosfets.


* Assuming that the duty cycle never approaches 100%

 

[mading2018]

Thank you guys, it seems to work now, thanks to your instructions. My only concern is that the current input waveform have spikes, it should be more sinusoidal with the voltage waveform I think. But maybe it is still okay.

 

[alec_t]

My only concern is that the current input waveform have spikes, it should be more sinusoidal with the voltage waveform I think. But maybe it is still okay.

I think that's about as good as it gets. Linear Tech's own demonstration circuit for the chip gives input current spikes.