LED Strip lights (2 Amps) Short Fade on / Fade Off effect

[ThomsCircuit]

But be sure to not leave any isolated planes l

I now have 3 pours on the top layer.
Ground Plane. Helps the Emitter trace on the TIP
Collector Plane. To help the Collector trace on the TIP
12V Plane. To beef up the + rail where suggested.
Also relocated a few components and traces to allow the pours to flow.
NOTE: The bottom GND pour is removed for clarity.

 

[eTech]

I now have 3 pours on the top layer.
Ground Plane. Helps the Emitter trace on the TIP
Collector Plane. To help the Collector trace on the TIP
12V Plane. To beef up the + rail where suggested.
Also relocated a few components and traces to allow the pours to flow.
NOTE: The bottom GND pour is removed for clarity.
View attachment 135222

Much better…

 

[ThomsCircuit]

I made a small change. Posting to be certain im correct.
This circuit is a negative (-) junction that sits between the relay switch and the light (LEDS) negative terminal
While the PWM circuit requires 12v+ the light is already connected to 12V+ it does not need a connection to it from this circuit.
All connections are from the same power source

 

[rjenkinsgb]

You still have all the interconnection traces on the top rather than the bottom???

 

[rjenkinsgb]

This is more like I'd expect it to look, based roughly on your component placement; no thin tracks, main interconnections solder side & full top groundplane.

 

[ThomsCircuit]

This is more like I'd expect it to look

Having the interconnections along with the V+ on top & GND on bottom is how I was shown.
If I make the tracks wider than the drill holes Design Spark give Desing Check rule error.
I usually only do top and bottom full GND pours. This is the first time doing different pours on a single plane.

 

[ThomsCircuit]

Where did C4 come from?

 

[rjenkinsgb]

Having the interconnections along with the V+ on top & GND on bottom is how I was shown.

I'd possibly agree if you were doing surface mount with components on the top, but not for conventional through-hole designs.
I very much doubt you would find any commercial products designed like that.

Where did C4 come from?

Power decoupling, just added out of habit with a [hopefully] functional design...

 

[rjenkinsgb]

If I make the tracks wider than the drill holes Design Spark give Desing Check rule error.

That sounds like a bug or something messed up in the configuration? Tracks the same as or larger than the pad widths are not uncommon in power circuit deigns.

 

[ThomsCircuit]

Discussion.
Can I have tracks that funnel down to the drill hole size?
OK I see your remarks. Ill make the tracks wider. I use JLCPCB for board design.
Here is what I found in reguard to the "drill back off check"

So why do we have a "drill backoff" check?
Some users with advanced in-house processes still have versions of the photo-plotters which 'draw' or plot each line and shape by optical means. The line width and shape are controlled by the optics and aperture and the path determines the shape.
The process still does the copper etch before the drilling stage, but this generation of plotter will reproduce any tracks as drawn by the designer into the pad 'hole' area. The consequence of this is that the high speed small diameter drills will break if they meet a target hole with a partial copper content. Drill Backoff is a process built into DesignSpark PCB to remove and clear the pad hole of tracks.

-----------------------------------------------------------
Ive removed the 12v pour because of a re-design.
I left the small collector pour & the GND pour as it aids making the TIP122 tracks as wide as possible

 

[ThomsCircuit]

Power decoupling, just added out of habit with a [hopefully] functional design...

should I add one to the 555 between pin 1& 8?

 

[ThomsCircuit]

Modified with 0.1uf on IC's and wider (35) (what ever that number means) tracks

 

[rjenkinsgb]

The process still does the copper etch before the drilling stage, but this generation of plotter will reproduce any tracks as drawn by the designer into the pad 'hole' area.

I believe that could only apply to single-sides board processes, as for plated-through hole boards the drilling is done before etching so the electroplating can take place - the un-etched copper is required for that process, to provide electrical continuity to all the holes.

I've never heard of it as a restriction, going back to when I was first changing from hand-taping PCBs to CAD systems, or even for single-sides boards.
Is it something that can be disabled in the design rule checks?

 

[ThomsCircuit]

Is it something

Yes. I disabled it. Thank you for clearing that up. It was a pain.

 

[eTech]

You still have all the interconnection traces on the top rather than the bottom???

Is that a problem?

 

[rjenkinsgb]

Is that a problem?

It's just bad practice, a bad habit to get in to.

It's not all that important with this design, though it could make soldering harder, and [if the PCB manufacturer was less than perfect] cause failures or reliability problems, as all topside component connections are reliant on the plating being good and solder fully flowing.

And with more complex, higher frequency or small signal boards, one of the purposes of a ground plane is to provide screening between the components and other signal tracks that pass underneath them.

Having the signal traces on the top side totally defeats that.

Surface mount and multilayer or stripline / dead bug etc. boards are obviously different, but for conventional components I have never seen a single commercial board with the tracks swapped. Some at one time occasionally had an image of the underside printed on the top to show connectivity, but the copper was still on the underside.

 

[eTech]

Modified with 0.1uf on IC's and wider (35) (what ever that number means) tracks
View attachment 135232

There is no reason to have wide traces on every track route. Only the tracks I mentioned earlier. There is also nothing wrong with having used a 12v plane on top as well. But to get with your project leave as is.

For future reference:

The reason the tracks shouldn’t be as wide as the pad diameter is that the track will act as a heat sink and solder will be drawn toward the track instead of collecting around the pin and pad area. Using a pour avoids this because a thermal pad will be used instead, the pad spokes can be widened appropriately to satisfy the power requirements.

During my early board taping and CAD days multiple planes were used on top were used when necessary. Nothing wrong with doing that.

 

[eTech]

It's just bad practice, a bad habit to get in to.

It's not all that important with this design, though it could make soldering harder, and [if the PCB manufacturer was less than perfect] cause failures or reliability problems, as all topside component connections are reliant on the plating being good and solder fully flowing.

And with more complex, higher frequency or small signal boards, one of the purposes of a ground plane is to provide screening between the components and other signal tracks that pass underneath them.

Having the signal traces on the top side totally defeats that.

Surface mount and multilayer or stripline / dead bug etc. boards are obviously different, but for conventional components I have never seen a single commercial board with the tracks swapped. Some at one time occasionally had an image of the underside printed on the top to show connectivity, but the copper was still on the underside.

Sorry I disagree. Back in the day I, also designed (taped/cad) boards for mixed analog/digital failsafe electronics and we did it differently.

 

[ThomsCircuit]

Thank you all so very much. Ive learned a great deal. I'll get the TIP & other components and Bread board this up.

 

[ThomsCircuit]

I did what I could to create islands for each pin of the transistor and getting as many spokes as i can around the pads. these are on the top layer. Except the GND track
3 GND pour
2 Collector pour
1 Emitter pour
There is also a positive and GND pours. And a full GND pour on the bottom
NOTE: I put the single LED back with a 1k resistor