library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity testVHDL is
Port ( x : in STD_LOGIC;
y : in STD_LOGIC;
F : out STD_LOGIC);
end testVHDL;
architecture Behavioral of testVHDL is
begin
process(x,y)
begin
-- Compare to truth table
if ((x='0') and (y='0')) then
F <= '0';
else
F <= '1';
end if;
end process;
end Behavioral;