Eagle - Hints & Tricks

[jpanhalt]

This is a new problem with Eagle. I hope it is not considered OT, as this thread has sort of become a place for Eagle problems.

In Eagle 4.14, I created a "New Schematic" using a standard FRAME and DOCFIELD from the Eagle library. I also added a few very common parts to speed up the process of making a new schematic. In practice, I would just open New Schematic, save it under the name of whatever new thing I was doing and proceed. Never a problem.

I updated to Eagle 5.2 recently, and find that it is automatically and sporadically changing information in the DOCFIELD. It deleted the top field ("Company Name"), changes the title field, and totally screws up the date field. Everything except the date field can be fixed. I use the date field to list the initiation date, and the rev. field to keep track of changes. When Eagle deletes or changes the Date field, I have no way at present to recover that information.

I put in a call to Cadsoft, but the technical expert is on his boat, and a 3-way conversation with the receptionist, tech person via ship-to-shore, and me just wasn't getting anywhere.

Has anyone had a similar problem? Is there a cure?

John

 

[jpanhalt]

Here is an answer to my own question in case others have faced something similar. This is after discussion with tech service at Cadsoft. He didn't say how the fishing was.

Apparently, the Frames library has different attributes/associations in 5.2 than in 4.1X. My "New_schematic" was created with 4.14 and saved as a .sch file, not .lbr file. When it is in use, if I "update" libraries, Eagle finds the name for the symbol I used ("Frame2, Dina3_L") in 5.2 and adds 5.2's attributes, which don't work well with data entries made in 4.14. That is just a working hypothesis.

The solution is to create your personal frame in your personal library with a different name. If it is done with 4.1X, it will keep those attributes when used with 5.2, because it will be treated as a different symbol.

This is a bit arcane, but hopefully it will help someone else.

John

 

[Boncuk]

Hi Silvarblade,

the default scale setting in the print menue is normally set to the value '1'. This means a truly scaled image of the factor 1. Any other factor will result in a print of the PCB according to the setting, e.g. scale factor 1.5 will enlarge the image to Lx1.5 X Wx1.5.

Please check the scale factor value.

Hans

 

[3v0]

Eagle just released 5.3.

There are two nice things that caught my eye regarding routing traces.

The first is that if you hold down the shift key the new trace will be the same width as the trace you are extending.

The other is that the center of off grid pads are now snap points. This makes routing traces to components that do not conform to the grid or have had their location tweaked easier.

3v0

 

[Boncuk]

This makes routing traces to components that do not conform to the grid or have had their location tweaked easier.
3v0

... still resulting in angle error messages when performing a DRC. I route off grid elements using 1mil to end the trace at the off grid pad. This method ensures equal trace distance between pads and doesn't result in angle error messages.

See example board.

Hans

 

[3v0]

I turned off the angle check in the DRC. Maybe it is time to turn it back on.

 

[Boncuk]

An easy way to make a bridge rectifier with single diodes

Hi All,

1N4XXX are available in almost every electronics freaks junk box.

Here is an easy way to "construct" a bridge rectifier using four of those.

- create a symbol at a 45 degree angle naming the pins as you prefer (e.g. A and C)
- use the already available package to create a device.

- place the four diodes in your schematic with the 'pins displayed' to match each neighbor's pin.

This method has some speed advantages in design:

The "bridge rectifier" is clearly to determine as a bridge rectifier, other than horizontally or vertically drawn diodes.

The diodes are already connected in logic sequence. So just the external nets have to be drawn.

With the pins display disabled it looks like a commonly used bridge rectifier symbol.

You are free to place the single diodes according to your preferance.

And this is how it looks in the schematic and on the PCB design.

Regards to all

Hans

 

[jpanhalt]

DRC Problem

I am about to send my first PCB to an outside board house. It is a power supply and after connecting various pads, I overlaid a large rectangle for a heat sink. Like this:






That fails DRC with numerous overlap errors. I know how to get around it (I think) with a Pour dialog, but that would become tedious, if one had several to do on the same board. Is there another way? Version 5.2 does not allow me to simply name the rectangle as a net.

Thanks. John

 

[3v0]

That fails DRC with numerous overlap errors. I know how to get around it (I think) with a Pour dialog, but that would become tedious, if one had several to do on the same board. Is there another way? Version 5.2 does not allow me to simply name the rectangle as a net.

Thanks. John

Create the rectangle using POLYGON netName. It is not tedious.

 

[jpanhalt]

I tried doing that earlier this AM. Problem was that some of the devices being heat sinked have outlines that don't fill completely, and for some strange reason, the polygon for that part of the circuit (N$3) was included in the ground fill.

EDIT: Forgot about ranking. Now it works. (It was 3AM local time.)

I definitely need to play with that some more. I don't want to have to create a bunch of new devices.

The tedious part is related to my practice of covering about 1/2 of the thermals for ground pins for high-current devices, like a Schottky diode, capacitor, etc. to get effectively a wider PCB trace. Eagle gives no control over the thermal and it seems a bit odd to have 4 little thin connections on a trace that is otherwise 150 mils. Eagle doesn't give the option of having thermals for some devices and not others.

Another option is to find out if the board producer can ignore overlap errors. That question has been sent to two of the less expensive houses.

John

 

[Boncuk]

Hi John,

may be this one will be a satisfying solution for you.

Use either layer29(tStop) or layer21(tPlace) to outline the heatsink.

Using tStop there will be no soldermask printed on the PCB within the area of the polygon.

This layer is useful if you want to keep copper areas on the board reserved for cooling purposes. (see attached example).

PCB manufacturers normally don't care for overlap and distance errors. It's the customer who has to provide an error free board layout.

BTW. There must also have been an angle-error message in your design.

Hans

 

[jpanhalt]

Hans,

Thanks for the advice. There were some angle errors. I turned them off while dealing with the 147 overlap errors. It was a learning experience. I certainly won't use the rectangle tool for that purpose again.

John

 

[Gayan Soyza]

Hello I also like to join to this thread,

I have a small problem.

How to increase the width of the Top Layer (Dimensions layer) components? Without going to each components package & adjust the size one by one.

Is there any easy way to do this?

 

[BeeBop]

Hello I also like to join to this thread,

I have a small problem.

How to increase the width of the Top Layer (Dimensions layer) components? Without going to each components package & adjust the size one by one.

Is there any easy way to do this?

Do you mean the width of the pads for components?
With your board open choose design rules from the edit menu. Click on the tab restring. You will see right away how to get what you want.

 

[Gayan Soyza]

Hi I mean the Top Place layer & not the pads.

Here is that.

 

[Boncuk]

Hi Gayan,

I'm afraid you'll have to edit the component in the libary editing the package. That's really no big deal.

This a fast an easy way: Disable the pads (layer17). Group the entire package outline and change the line width using "change width" and apply the change using the right mouse button.

Remark: If the text(s) >NAME and >VALUE appear in the group too, it doesn't matter at all. Letters thickness is changed by "change ratio"

You can also change the ratio of part description in an entire schematic by grouping it completely and change e.g. the ratio of part numbers and values also using the right mouse button.

The standard setting for ratio is 8. I prefer changing the ratio to 6. The schematic looks much cleaner with lettering not that bold.

Regards

Hans

 

[Gayan Soyza]

Hi Hans I tried that fast method but it won't work.

"This a fast an easy way: Disable the pads (layer17). Group the entire package outline and change the line width using "change width" and apply the change using the right mouse button."

I group the entire package & change its width using change tool & applied change group but its width never changes

 

[jpanhalt]

Gayan,

Are you asking about changing the width of the component (i.e., its area on the board), not the width (thickness) of the lines that outline the component?

John

 

[Gayan Soyza]

Hi John

I need to increase the width (thickness) of the lines that outline the components.

For the time being I'm doing like this.Going every components library package & edit its width (thickness) one by one.

Is there any easy way of doing this?

 

[Gayan Soyza]

See this picture, I want to increase the width (thickness) of that lines.That is the TPlace layer (21).