Hello, i need a help and advices in VHDL code writting. I got a problems in my final years project. i try to make it generally and as simple as i can, perhaps someone may help me.
i have three component build in single source file. let say;
component adder (porta, portb, cin, cout, sum)
comonent subtract (porta, portb, cin, cout, sum)
component and (porta, portb, sum)
so, each component have it own architecture, etc as suppost la....
now i would like to make a master architecture where this master will call what component should be used to its input base on ctrl signal. eg;
if ctrl = "01" then used component adder to perform the operation
if ctrl = "10" then used component subtract to perform operation
if ctrl = "11" then used component and to perform operation
i cannot used case, i don't know what the problems, but i can only make case run in process(), but component woun't run in process().
so, my solution is introduces ctrl in each component, so, if the ctrl signal is not same as it setting, the component will put it's output to 'X'. this technique will make all component capture the input port at the same time, but only the corresponding component to ctrl signal will produces the output. However i failure to synthesis this design.
the idea i think is like in c programming, we can have a subroutine, and when we need it just pust a call instruction.
is there another way to make the idea work. as long as all component work base on ctrl signal. mean, the design should lisen to external input signal (ctrl) before it make it decision on what operation it should perform on its input (porta and portb and cin).
i have three component build in single source file. let say;
component adder (porta, portb, cin, cout, sum)
comonent subtract (porta, portb, cin, cout, sum)
component and (porta, portb, sum)
so, each component have it own architecture, etc as suppost la....
now i would like to make a master architecture where this master will call what component should be used to its input base on ctrl signal. eg;
if ctrl = "01" then used component adder to perform the operation
if ctrl = "10" then used component subtract to perform operation
if ctrl = "11" then used component and to perform operation
i cannot used case, i don't know what the problems, but i can only make case run in process(), but component woun't run in process().
so, my solution is introduces ctrl in each component, so, if the ctrl signal is not same as it setting, the component will put it's output to 'X'. this technique will make all component capture the input port at the same time, but only the corresponding component to ctrl signal will produces the output. However i failure to synthesis this design.
the idea i think is like in c programming, we can have a subroutine, and when we need it just pust a call instruction.
is there another way to make the idea work. as long as all component work base on ctrl signal. mean, the design should lisen to external input signal (ctrl) before it make it decision on what operation it should perform on its input (porta and portb and cin).
