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My son need help with his circuit design!!!

Gmoneys

New Member
My son is graduating next year with a EE degree.
He can't get his design project to work

He is using a Ti chip (LMG5200MOF -TRANS) but I suspect there is something wrong
he is also using

the problem that he is having is that he is expecting an output of 12V he is actually getting -122.8mV

more info:
Class D Circuit
48V into Vin
5V into Vcc
Pulse width Modulation (PWM) into the HI and LI
LC circuit from SW output (12V) and (8A)
PWM Frequency is 2048kHz
Need decoupling capacitors in Vin & Vcc

thanks everyone in advance for your help!!

G'
 

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The 48V supply is not making it to the input at pin 1 of the IC?

Try deleting the connections from the 48V source and re-doing them, it looks like one of the "wires" missed a device terminal?
 
Also the +5V power supply is not reaching pin 6 (Vcc).
I assume this design for for a buck regulator. If so using a half bridge driver seems a strange way to do it.
Also the value of L2 seems to be very high and the value of C23 seems very low.
IF MY UNDERSTANDING OF THE PWM WAVEFORM IS CORRECT I think the it is 500 Mhz wth a 50 % duty cycle. This seems to be be too high a frequency for this device. (I have never used this device but it does not seem to agree with the spcifications on the data sheet.)

Les.
 
If your son's circuit is exactly as in the post #1 schematic there are problems. He needs to understand the operating conditions for that IC as set out in the datasheet.
In particular, the Vcc pin needs a decoupling capacitor and dead-time is needed between the HI and LI signals.
The simulation as per post #1 won't work because (amongst other things) V8 and V9 have a pulse frequency of only 0.1Hz.
 
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The output filter LC values seem way off. Stray C is >> the .01 pF shown.
If its for clock reduction, removal, in output, the 2 Mhz per your PWM rates,
try something more like 10 uH, 630 pF. A calculator for cutoff freq -


With regards to earlier comments on dead time, here is a drawing of what that means, focus on ph1 and
ph2, as you can see they are never both high at the same time. If they were then the output stage of the
5200 would have both fets on shorting the power supply to ground and destroying parts.

1697544611652.png


1697544589244.png




Regards, Dana.
 
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My son is graduating next year with a EE degree.
He can't get his design project to work
I feel good that a parent is trying to help their child. I am disappointed that the next generation of engineer relies on his parent to seek homework help.

A design project is usually a multi-tier project. In this case, understand
- the concept of SMPS
- understand the chip (datasheet)
- understand the simulator and the required inputs to the chip
- understand feedback loops (if feedback external to the chip is required)
- understand minimum load requirements on the chip - if any)
- understand idiosyncrasies of the simulator (like not necessarily making a connection to a node, even though it looks like a connection is made (often caused when moving components or wires - erase and redraw wires to insure the node connects.

I think there is a misunderstanding on the input signals (at minimum) and possibly minimum load and unconnected nodes.
 
I feel good that a parent is trying to help their child. I am disappointed that the next generation of engineer relies on his parent to seek homework help.

A design project is usually a multi-tier project. In this case, understand
- the concept of SMPS
- understand the chip (datasheet)
- understand the simulator and the required inputs to the chip
- understand feedback loops (if feedback external to the chip is required)
- understand minimum load requirements on the chip - if any)
- understand idiosyncrasies of the simulator (like not necessarily making a connection to a node, even though it looks like a connection is made (often caused when moving components or wires - erase and redraw wires to insure the node connects.

I think there is a misunderstanding on the input signals (at minimum) and possibly minimum load and unconnected nodes.
he has been seeking help from others and the professor as well but no one has been able to...
 
I feel good that a parent is trying to help their child. I am disappointed that the next generation of engineer relies on his parent to seek homework help.

A design project is usually a multi-tier project. In this case, understand
- the concept of SMPS
- understand the chip (datasheet)
- understand the simulator and the required inputs to the chip
- understand feedback loops (if feedback external to the chip is required)
- understand minimum load requirements on the chip - if any)
- understand idiosyncrasies of the simulator (like not necessarily making a connection to a node, even though it looks like a connection is made (often caused when moving components or wires - erase and redraw wires to insure the node connects.

I think there is a misunderstanding on the input signals (at minimum) and possibly minimum load and unconnected nodes.

I hear Flyback is hiring. :)
 
My son is graduating next year with a EE degree.
He can't get his design project to work

He is using a Ti chip (LMG5200MOF -TRANS) but I suspect there is something wrong
he is also using

the problem that he is having is that he is expecting an output of 12V he is actually getting -122.8mV

more info:
Class D Circuit
48V into Vin
5V into Vcc
Pulse width Modulation (PWM) into the HI and LI
LC circuit from SW output (12V) and (8A)
PWM Frequency is 2048kHz
Need decoupling capacitors in Vin & Vcc

thanks everyone in advance for your help!!

G'
Hi
In addition to other members comments, go to this link:


There you can download "LMG5200 PSpice Transient Model (Rev C)".
This includes a PSpice design that is close to the design you are attempting.
Load and run it, it will help you understand the circuit behavior.
 
There you can download "LMG5200 PSpice Transient Model (Rev C)".
Isn't that what the TS is using in the post #1 sim?
 
Departing from datasheet and vendor App notes for SMPS demands experience not normally taught at Univ. Every part has a reason and every layout choice as well. Understanding these reasons is a key step to custom design before embarking on your own interpretations of the datasheet.

The theory may include transmission line design, Control System Theory with load dependence, EMI interference, parasitic effects, choosing a dead time of the bridge ~ 1%+ of the switching rate cycle and many more advanced items.

Advanced speed switches operating > 1MHz are difficult due to the 100 MHz BW (1%) implications of dead time.

Compromises on efficiency are tradeoffs with cost and complexity. SMPS designs can be non-trivial with complex issues.


When dealing with TI chips, the experts will not be the Prof or TA but the TI Product Support groups with a free login. Learning who and how to get expert advice is key to learning how to advance your skills faster.,
1697600669291.png
 
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