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Timer - 5 min on, 2 sec off

crutschow

Well-Known Member
Most Helpful Member
#41
I want to know when it happens! My idea was to use another 555 timer that will trigger in bistable mode when the mosfet resets (powers off).
You can use another 555 for that, or simpler is a two NAND gate (1 package) set-reset latch circuit.
 
Thread starter #42
You can use another 555 for that, or simpler is a two NAND gate (1 package) set-reset latch circuit.
I tried and succeeded to some extent, I tried to copy samples from the internet but couldn’t understand why sometimes it falsely triggers when I first power on the circuit. Remember I’m not an engineer, so I get lost easily.

I don’t want to feel like I’m taking advantage, so if you don’t mind, I want to pay you for your time, in exchange for your help. If the NAND chip is a better choice I’m good with that. I just need a schematic so I can put it together! Please let me know what you think.
 

crutschow

Well-Known Member
Most Helpful Member
#43
You don't have to try to contact me, and I don't do this for pay -- it's my hobby. :)
I prefer answering all questions on the forum so everyone can benefit from the answers.

Below is the circuit with an added NOR-gate latch to indicate that the power has been reset (green trace).
V3 resets the latch (purple trace).
(A NOR-gate latch turned out to be simpler than a NAND-gate latch for the given signal polarities.)

R8 C3 act as a power-on reset for the latch.

1551132680401.png
 
Last edited:
Thread starter #44
I was watching some videos (trying to learn all I could about NAND NOR etc...), now looking at your new schematic it begins to make sense! Well if you cannot accept not even donations, then I can only use my words: THANK YOU!! I will put the circuit together tonight, and will follow up with results.
 

Pommie

Well-Known Member
Most Helpful Member
#45
Maybe you should try and fix the pi code. How often does it crash? Can you add a monitor of some kind that can print "entered x sub", "exited x" etc. Can you monitor free memory in case it's a memory leak?

Mike.
 
Thread starter #46
You don't have to try to contact me, and I don't do this for pay -- it's my hobby. :)
I prefer answering all questions on the forum so everyone can benefit from the answers.

Below is the circuit with an added NOR-gate latch to indicate that the power has been reset (green trace).
V3 resets the latch (purple trace).
(A NOR-gate latch turned out to be simpler than a NAND-gate latch for given signal polarities.)

R8 C3 act as a power-on reset for the latch.
Ok, I'm back to report the outcome: PERFECT! Couldn't be any better! That's all, now it's complete! Thank you Crutschow :)

Maybe you should try and fix the pi code. How often does it crash? Can you add a monitor of some kind that can print "entered x sub", "exited x" etc. Can you monitor free memory in case it's a memory leak?
Yes that would be the correct way of doing things, if it crashes it means there's a bug somewhere. But the problem is very rare, it won't happen for 3 months, sometimes once a month... The code has been checked and my programmer couldn't find anything wrong. Maybe it was overlooked, or maybe it has to do with something that turns on in the building and causes some kind of interference or noise in the power supply line... or maybe the SD card could be acting up, or the RPI itself... it could be so many things, so I'm not even sure what's causing it. I have planned to begin swapping some parts, including the RPI, and I want to see if it helps. If the problem continues, then I'll dig deeper into the code.
 

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