Hi again,
Tony:
That is one of the things we are trying to figure out
Wizard:
Are you sure you meant to say that the two capacitor expression replaces the resistor in the continuous time integrator?
One of the things that puzzled me a bit was that expression about the gain of the continuous time integrator:
"Continuous integrator gain at input frequency"
But we can only know this gain if we include the resistor or just an expression, for example:
1/(s*R*C) => 1/(j*w*R*C) => wo/(j*w)
So i guess what they are saying is that the gain is:
0.5*C2/(C1+C2)*wo/(j*w)
but i have to question how we establish what wo is.
wo must come from the two capacitors also, because that's all we really have to work with.
Sound right to you or no?
Perhaps this sim will help inform the discussion:
View attachment 92548
It is clear from the plot that since C2 = 10 x C1 in this example, it takes 10 steps (10 x the pulse-period) for C2 to charge up to the same voltage that is applied to C1. The output can be deduced as V(out) = -V(in) * (C1/C2) * time/pulse-period.
My simple analysis and assumptions still hold true.Still dont know who told you 0.5
There are two breakpoint frequencies.
e.g. GBW product and drive current and capacitive load
Lets assume you need very low Iin and Vio , true for all integrators.
Then assume you want rail to rail in-out.
This leads to output ESR in the range of Rs=1K
Switch rate determine open loop gain from GBW.
If Switch interval, T1 is slower than RsCfb then Vout =-Cin/Cfb*Vin for initial step.
Slew rate is limited by both gain and ESR*Cfb
Ignoring the DC gain from Cap leakage....
What BW are you using?
e.g. Good OA https://www.digikey.com/product-detail/en/LMV341MG/NOPB/LMV341MG/NOPBTR-ND/566645
good film caps can give T2 leakage time constants in minutes.
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