SMPS MOSFET issue

[Aether32]

Greetings,

I am working on a flyback smps.

Currently I am having a problem with the mosfet switching, the mosfet itself won't mirror the drive
signal from the PWM controller, only a distorted pulse appear. I am sure the PWM controller is able
to drive the mosfet without a problem as the input capacitance of the mosfet is max. 750 pF and
the allowed capacitance for the PWM controller is 1 nF.

I guess the "distorted" wave at 0 V AC doesn't tell much, but check the huge spike over the transistor @10 V AC, it's like 50 V, shouldn't be so high, it looks like the transistor is operating wrong and the spike from the 0 V screen gets amplified.
The voltage between drain and source shouldn't be higher than 10 V * sqrt(2) (+ possible spikes).

I've tried several transistors now, still this strange issue, the GS voltage and everything seems to be correct...

Input from mains: 230~ V AC -> 325~ DC
Switching frequency: 450 KHz
output voltage: 19 V
output current max.: 4.74 A

parts:
PWM controller: UC3842
Mosfet: 2SK2700

The PWM controller receives power from an external power supply.

Circuit schematic and signal captures from the circuit are attached.

In the signal captures the yellow line is the switching from the PWM controller, blue line is the drain-source voltage @ 0 V AC and 10 V AC

Any pointers are welcome

 

[Claude Abraham]

There is no snubber across the FET, one should be added. The duty factor is just under 50%, so the voltage from drain to source during the PWM off time, will be nearly twice 10*sqrt2, or 28.28V, plus any overshoots incurred w/o snubbers. Also, the UC3842 is a current mode control IC, yet I see no slope compensation included. Do you plan on adding it? Just some suggestions. I presume that the supply operates in continuous conduction mode, and that the inductance of the flbk xfmr is sufficient to assure ccm operation. BR.

 

[Archion]

Error, delete this message.

 

[Aether32]

There is no snubber across the FET, one should be added. The duty factor is just under 50%, so the voltage from drain to source during the PWM off time, will be nearly twice 10*sqrt2, or 28.28V, plus any overshoots incurred w/o snubbers. Also, the UC3842 is a current mode control IC, yet I see no slope compensation included. Do you plan on adding it? Just some suggestions. I presume that the supply operates in continuous conduction mode, and that the inductance of the flbk xfmr is sufficient to assure ccm operation. BR.

Yeah, it runs in continuous conduction mode, the flbk xfmr is set to 585 uH, current ripple factor is 0.5.
A snubber across FET should fix some of the spike issues i am having, and i should probably try to add a slope compensation for the current measurement.

Thanks for your input.

 

[indulis]

OK… a couple of things.

I don’t see any soft start circuitry.

The 3842 has an internal 34V zener on Vcc, but the MOSFET’s max gate voltage is ±30V.

The opto has a CTR from 50-600%. The loop compensation will be a whole lot easier with a narrower range and even better if you can find one with a CTR of <100%.

The duty factor is just under 50%, so the voltage from drain to source during the PWM off time, will be nearly twice 10*sqrt2, or 28.28V…

The duty cycle has nothing to do with it. In a flyback, the primary MOSFET’s drain “plateau” voltage will be the secondary voltage reflected back thru the transformer (coupled inductor) by it’s turn ratio plus the primary voltage plus leakage spikes.

There’s something wrong with the first scope pic… the gate voltage should be high when the drain voltage is low, and why is CH2’s reference at the drain plateau?

What is the input voltage in the second pic

 

[Aether32]

OK… a couple of things.

I don’t see any soft start circuitry.

The 3842 has an internal 34V zener on Vcc, but the MOSFET’s max gate voltage is ±30V.

The opto has a CTR from 50-600%. The loop compensation will be a whole lot easier with a narrower range and even better if you can find one with a CTR of <100%.

The duty factor is just under 50%, so the voltage from drain to source during the PWM off time, will be nearly twice 10*sqrt2, or 28.28V…

The duty cycle has nothing to do with it. In a flyback, the primary MOSFET’s drain “plateau” voltage will be the secondary voltage reflected back thru the transformer (coupled inductor) by it’s turn ratio plus the primary voltage plus leakage spikes.

There’s something wrong with the first scope pic… the gate voltage should be high when the drain voltage is low.

What is the input voltage in the second pic

Is a startup circuit really necessary?

Hmmm, i thought the 34 V zener only had to do with voltage limitation on the Vcc input to prevent the IC from getting too high voltage.

Yeah, the first scope picture is weird indeed, looks like signal gets distorted somehow.

The input voltage in the second picture is 10 V AC.

 

[indulis]

Without soft start, I limit is the only thing that limits input current, so youre starting into a hic-up and hoping it will be able to "ratchet " itself up. When you get to a full power start-up, you might (probably will) have problems. You will find that virtuallly every SMPS has soft start to clamp the error amp, hence duty cycle, to limit current and have a "graceful" start-up.

Why not feed the input to the transformer directly with DC until most of the bugs are worked out?

...i thought the 34 V zener only had to do with voltage limitation on the Vcc input to prevent the IC from getting too high voltage.

Yes, but what will limit the gate voltage to the MOSFET?

 

[Ubergeek63]

Greetings,

I am working on a flyback smps.

Currently I am having a problem with the mosfet switching, the mosfet itself won't mirror the drive
signal from the PWM controller, only a distorted pulse appear. I am sure the PWM controller is able
to drive the mosfet without a problem as the input capacitance of the mosfet is max. 750 pF and
the allowed capacitance for the PWM controller is 1 nF.

I guess the "distorted" wave at 0 V AC doesn't tell much, but check the huge spike over the transistor @10 V AC, it's like 50 V, shouldn't be so high, it looks like the transistor is operating wrong and the spike from the 0 V screen gets amplified.
The voltage between drain and source shouldn't be higher than 10 V * sqrt(2) (+ possible spikes).

I've tried several transistors now, still this strange issue, the GS voltage and everything seems to be correct...

Input from mains: 230~ V AC -> 325~ DC
Switching frequency: 450 KHz
output voltage: 19 V
output current max.: 4.74 A

325V to 19V ~ 15:1 so you want a 8:1 or so transformer. 19V x 8 is 150V reflected plus your 325V rail is 475V on the drain that you can do nothing about. Add to that the spike from the leakage inductance that you can cut back with a snubber is what you should see on the drain at full supply...

from your description, it seems that you are neglecting the transformer reflected voltage.

Dan

 

[indulis]

325V to 19V ~ 15:1 so you want a 8:1 or so transformer.

You know as well as I that coupled inductors (a.k.a. flyback transformers) and transformers have completely different design procedures. Without knowing the cores inductance factor, cross section, material... etc. and at what point the unit is to enter CCM, how did you cone up with those numbers?

 

[Aether32]

19V x 8 is 150V reflected plus your 325V rail is 475V on the drain that you can do nothing about

Yes, you are right, i forgot the reflected voltage, after my calculations it should be max 540ish V over the FET when it's turned off.

------------------

The problem i am having is the actual waveform that is generated, it's not really resembling a square-like wave or even close to one, it's a half-sine thingy, and the sine-like thingy peaks ridiculuously high with like 600-700 V @ 110 V AC. I think the problem is the FET, it's not really mirroring the actual input signal from gate. Most likely it's not receiving enough juice for it to switch properly (charging of internal capacitors), or the FET is getting too high voltage on the gate (i tested it with a test circuit, the positive side of the pulse became distorted when I pushed more than 2 V over GS, this is strange because the GS voltage must be 4 V to be "on" at some temperatures).

Yes, but what will limit the gate voltage to the MOSFET?

Vcc will limit it, but the PWM controller is only running at 10 V at the moment and it will not run at any lower voltages.

--------------------

 

[indulis]

Yes, you are right, i forgot the reflected voltage, ...

Re-read post #5... did you miss it there?


OK... while the PWM is running with 10V, apply and slowly increase a DC voltage to the "transformer". At what point does the gate signal "screw-up"? What does the current sense signal look like when that happens?
Just curious... is this your first flyback, or are you familiar with what "should be happening"?

 

[Aether32]

Re-read post #5... did you miss it there?

Yes, must have missed it there, two posts came too close to each other

OK... while the PWM is running with 10V, apply and slowly increase a DC voltage to the "transformer". At what point does the gate signal "screw-up"? What does the current sense signal look like when that happens?

The signal pretty much screws up as soon as you apply voltage to the transformer, the current sensing is a mess with spikes going from 0 -> 0.4 V.

Just curious... is this your first flyback, or are you familiar with what "should be happening"?

This is my first flyback, but i've read a lot about the theory behind it.

 

[indulis]

OK... a little more info on the "transformer"...

What is:
Core?
Material?
Inductance factor?
Primay turns and wire AWG?
Secondary turns and wire AWG?
Vcc turns?

 

[Aether32]

Core?
EFD-30 3F3

Material?
Ferrite 3F3 core with permeability 1560.
Have introduced a air-gap of 0.1 mm after calculations.

Inductance factor?
Primary inductance is calculated at 584 uH
And Volt-second 266 Vus

Primary turns and wire AWG?
33 turns with 3 strands of 0,3 mm copper wire (close to AWG31)

Secondary turns and wire AWG?
4 turns with 35 strands of 0,3 mm copper wire.

Isolation is 3 layers of Kapton tape.

Vcc turns?
Not sure I understand what turns you are talking about? :/

 

[indulis]

Vcc turns?
Not sure I understand what turns you are talking about? :/

Your Vcc winding ( also known as an "aux" or "house keeping" winding) in the primary.

Where and how did you gap the core... center leg or both outer legs?

Inductance factor... with 585µH and 33 turns (seems low, how high is the flux running) that would work out to be ~ 536 Al (nH)

BTW Ferroxcube has an off-the-shelf EFD-30 3F3 with an Al(nH) of 630 ±10% or Al(nH) 400 ±5%, for the latter, you'd have to increase the turns, but your max flux will come down.

It's still very troublesome that the gate signal goes to pot right after you apply a voltage to the "transformer"… you could disconnect the transformer and replace it with a resistor to see if you can draw any current thru the MOSFET. If that doesn't work, then there's something wrong with the FET.

 

[Aether32]

Your Vcc winding ( also known as an "aux" or "house keeping" winding) in the primary.

Where and how did you gap the core... center leg or both outer legs?

Inductance factor... with 585µH and 33 turns (seems low, how high is the flux running) that would work out to be ~ 536 Al (nH)

BTW Ferroxcube has an off-the-shelf EFD-30 3F3 with an Al(nH) of 630 ±10% or Al(nH) 400 ±5%, for the latter, you'd have to increase the turns, but your max flux will come down.

It's still very troublesome that the gate signal goes to pot right after you apply a voltage to the "transformer"… you could disconnect the transformer and replace it with a resistor to see if you can draw any current thru the MOSFET. If that doesn't work, then there's something wrong with the FET.

The core is gapped with kapton tape on the middle leg.

At the moment we (we are a group of 3 students) that have very little time left on this project :/ So to buy any new components are out of the question, sadly.

The AUX windings will have 4 or 5 windings.

However now we have some new results.

Using a breadboard we have simulated different frequencies on the MOSFET, and might give you a better picture of whats happening.

Yellow line is PWM to Gate
Blue line is Drain to Source.

Can you see the big difference on these two pictures? It seems the capacitance in the MOSFET dont have enough time or current to charge up and down again between each pulse. Will this cause the huge spikes in voltage that we are seeing?

We are thinking about reducing the frequency on the SMPS to see if this might be the problem?

 

[indulis]

The "turn-off" spike you see at the drain is from the leakage inductance... did you interleave the primanr and secondary windings? Also, the zener value in your primay snubber... not going to do a thing for you at these lower voltages. Also, put an RC snubber across the secondary rectifier diode.

This is basically a unit step function applied to an inductor type problem... why can't the FET pull the inductor low? Have you confirmed the primary inductance on a LCR meter or bridge?Are you sure the phasing of the windings is correct? Are you sure the MOSFET is good? I hate to ask, but I have too... are you absolutely sure it is connected properly? Have you "ohmed out" the MOSFET gate to drain to make sure nothing funny is going on?

Don't forget, at such low input voltages, your not going to get a whole lot of current thru the primary given your "on time"!!!

 

[Claude Abraham]

OK… a couple of things.

I don’t see any soft start circuitry.

The 3842 has an internal 34V zener on Vcc, but the MOSFET’s max gate voltage is ±30V.

The opto has a CTR from 50-600%. The loop compensation will be a whole lot easier with a narrower range and even better if you can find one with a CTR of <100%.



The duty cycle has nothing to do with it. In a flyback, the primary MOSFET’s drain “plateau” voltage will be the secondary voltage reflected back thru the transformer (coupled inductor) by it’s turn ratio plus the primary voltage plus leakage spikes.

There’s something wrong with the first scope pic… the gate voltage should be high when the drain voltage is low, and why is CH2’s reference at the drain plateau?

What is the input voltage in the second pic

"The duty cycle has nothing to do with it"???!!! Please tell me you're just joking! You're testing me right? The duty factor has EVERYTHING to do with it. The flbk xfmr must never be allowed to enter saturation. The volt-seconds/turn during the PWM ON time, must balance that in the PWM OFF time. As the duty factor increases, the OFF time reverse voltage must increase in order to preserve equal volt-seconds/turn.

That is why IC controllers like the 3842 family also offer a 3844/3845 version. The duty cycle is clamped to a 50% maximum in order to assure that the voltage reflected from secondary to primary does not exceed the input supply. Get out your reference material and please look it up. I'm not making this up. Seriously dude, you should be positive about something before firmly rebuking someone. What makes you think that you can tell me what's what?

Erring is NOT the problem. It's your cavalier attitude that needs adjustment, nothing personal. BR.

 

[Aether32]

The windings of the primary side is interleaved, and same for the secondary side. The secondary and primary side is isolated from each other with 3 layers of kapton tape.

The primary inductance is not measured, mostly because we don't have that equipment available.

The phasing of the windings are correct.

The MOSFET is connected correctly. Now all 3 have looked at the datasheet and at that it is connected.

Will disconnect the mosfet now and try to measure between gate and drain.

Would you then recommend to apply 230Vac directly and see what happens??

So you dont think this has anything to do with the frequency and the chargetime for the capacitance in the MOSFET?

The input capacitance of the MOSFET is 2000uF. Can it be that the PWM is not able to handle that?

 

[indulis]

The duty cycle at which a flyback converter is running at has NOTHNG TO DO WITH WHAT THE PLATEAU VOLTAGE ON THE PRIMARY MOSFET DRAIN WILL BE!!!!

How may references would you like to see before your convinced that it's Vout reflected thru the coupled inductors turns ratio + Vin???

Lloyd Dixon wrote a lot of good stuff on magnetics while at Unitrode/TI... read some of his thoughts on flybacks... in the mean time let me dig up a few links.

Seriously dude, you should be positive about something before firmly rebuking someone. What makes you think that you can tell me what's what?

Because I've been designing DC-DC for the past 19 years of my 35+ year career at the worlds #1 DC-DC prodcucer and the #4 AC-DC producer, that's why DUDE!