SMPS MOSFET issue

[indulis]

The input capacitance of the MOSFET is 2000uF.

That can't be right.

 

[Aether32]

That can't be right.

Correct.

2000pF, sorry about that.

 

[Ubergeek63]

You know as well as I that coupled inductors (a.k.a. flyback transformers) and transformers have completely different design procedures. Without knowing the cores inductance factor, cross section, material... etc. and at what point the unit is to enter CCM, how did you cone up with those numbers?

none of which effects the reflected voltage or the fact that leakage inductance exists.

they are actually pretty standard. the reflected voltage is always the product of the output and the ratio with 50-150V being the norm. all your concerns about procedures have nothing to do with it, he has a transformer that he is using and the question was about the spike, not if it is going to saturate.

He might not even know the characteristics to tell us. If you really want to be picky about it ask him what the coupling coefficient is.. fact is, it just does not matter. he has a transformer in his hands and it will either work or or it will not.

if it does not work he can ask for specifics then... as for now he was just freaking out over the spike.

Dan

 

[Aether32]

Not just the spike. Also the waveform that comes out from the PWM when applying voltage at the input. The square signal looks more like a sinus. Its those two problems that we are not able to solve :/

You have no idea how grateful we are that you are willing to help us out!

 

[Aether32]

When measuring resistance between gate and drain we dont get any results. Seems like it is infinite resistance. Not sure what you mean about "funny" results here. Could you explain that?

 

[indulis]

...in the mean time let me dig up a few links.

https://www.electro-tech-online.com/custompdfs/2010/05/AND8112-DPDF.pdf
page 1 between eq.1 and eq2

https://www.electro-tech-online.com/custompdfs/2010/05/AND8076-DPDF.pdf
page 4 under “Turn ration and Output Diode Selection”

https://www.electro-tech-online.com/custompdfs/2010/05/sluu087b.pdf
page 8 section 10

All say the same thing...

none of which effects the reflected voltage or the fact that leakage inductance exists.

I never said it did... I just asked how you came up with the ratio's without knowing more about the core, desired duty cycle... etc. Again as you know, with the flyback you can make the same output voltage with many different turns ratio's.

 

[Claude Abraham]

The duty cycle at which a flyback converter is running at has NOTHNG TO DO WITH WHAT THE PLATEAU VOLTAGE ON THE PRIMARY MOSFET DRAIN WILL BE!!!!

How may references would you like to see before your convinced that it's Vout reflected thru the coupled inductors turns ratio + Vin???

Lloyd Dixon wrote a lot of good stuff on magnetics while at Unitrode/TI... read some of his thoughts on flybacks... in the mean time let me dig up a few links.



Because I've been designing DC-DC for the past 19 years of my 35+ year career at the worlds #1 DC-DC prodcucer and the #4 AC-DC producer, that's why DUDE!

But Vout is determined by the duty factor. The FET turns on and energy builds up. The FET is switched off. The secondary winding discharges into the diode & output. The Vout value is simply Vin*(D/(1-D) times the turns ratio. In other words Vout is determined by Vin, the turns ratio, & the duty factor. To get high values of Vout, a large duty factor is needed, or turns ratio. SO it definitely matters as to duty factor. I'll go through my Lloyd Dixon references & post the info. I'm a SMPS diva myself w/ decades in the SMPS field & 32 yrs. in general EE.

 

[indulis]

When measuring resistance between gate and drain we dont get any results. Seems like it is infinite resistance. Not sure what you mean about "funny" results here. Could you explain that?

Nothing on the gate to drain measurment is good... if you had gotten a reading that would have been a problem, but since you didn't, that would suggest the FET is OK.

 

[Aether32]

Ok. We are now trying to switch FET, to one with a lower input capacitance. It has a 750pF input capacitance. And we will try to see what happens when we feed it 230Vac. To see if the snubber/zenerclamp will break down :/ And to see what the output voltage will be with a Rload like 25ohm or something in that area.

However we will go slowly up in voltage, try first at 50 Volt -> 100V -> 150V -> 230V .. If theres no smell, smoke or fire.. we will try to reach 230Vac on the input..

Wish us luck :/

 

[indulis]

But Vout is determined by the duty factor. The FET turns on and energy builds up. The FET is switched off. The secondary winding discharges into the diode & output. The Vout value is simply Vin*(D/(1-D) times the turns ratio. In other words Vout is determined by Vin, the turns ratio, & the duty factor. To get high values of Vout, a large duty factor is needed, or turns ratio. SO it definitely matters as to duty factor.

We can't violate the laws of physics... I 'm begining to think that we are talking about the same end result, just use to using a different road to get there. Calculating duty cycle at every input voltage on a wide input converter is a pain... so the shortcut is to use a formula that doesn't have it. Since Vin, Vout and N are all in there... an algebraic exercise/manipulation will no doubt lead to an equation with duty cycle in it.

 

[Aether32]

I can show you the result of ca 50Vac on the input, what the oscilloscope shows us.

We get a extremely high voltage spike over Drain - Source.

So now we dont have ANY idea how to proceed. Hope someone has a clue what could cause this.

 

[Ubergeek63]

Not just the spike. Also the waveform that comes out from the PWM when applying voltage at the input. The square signal looks more like a sinus. Its those two problems that we are not able to solve :/

You have no idea how grateful we are that you are willing to help us out!

at what load... sorry i am at work... under normal conditions your FET should ramp up and down over 125nS plus 50-150nS for the chip. What is not commonly known, and in fact a bit counter intuitive, is that under very light loads they can be slow...

it takes 8mA 440nS to discharge the 2.2nF osc cap 1.6V... reduce it to 500pF with a 4K resistor. the data sheet says it will be 30% dead time...

dan

 

[Aether32]

it takes 8mA 440nS to discharge the 2.2nF osc cap 1.6V... reduce it to 500pF with a 4K resistor. the data sheet says it will be 30% dead time...

That would have worked if we had used another IC like the 3844/45 (max duty cycle 50%), but we need to keep our max. duty cycle @ 37~%, a 4k resistor would give us a max duty cycle of 80%ish with the 3842/43 IC, too bad the 44/45s weren't available when we ordered the parts..