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Spot my ADC Mux Issue!

ACharnley

Member
Strange one here!

I've using a MCU which is 3 adc channels short, so I added 6x NMOS and 1x PMOS to switch the channels. In all cases I'm measuring either current over a resistor or voltage by a divider. The drive voltage is 3.6v (ignore the 3V0).
adc-aux.png


To prevent leakage through the alternative turned off nmos the voltage I found has to be kept below 0.4v as once it heads towards the 0.7v point there's enough leakage to make a difference to the read. The voltages and the current levels are all below 0.4v so the 3.6v drive comfortably turns on the 2N7002 NMOS.

The voltages are bang on, no problem there. Now, when reading the current over a 200mOhm resistor, 125mA the read is perfectly correct. Increase to 500mA, still correct. Grand!

However when using a 100mOhm resistor then the read is amplified. At 250mA the read is x1.2 larger. This increases so that mathematically it's something like [x1.4 - 50]

I measured the output at the resistor and it's correct, and then again at usbADC and it's definitely higher. My only thought was there's still some leakage through the NMOS, enough for the ADC to capture, so I turned on the MCU's 15k pull-down on the pin. It made no difference.

Any other thoughts?

Cheers!

Andrew
 
Any chance you can show total schematic of the interface to mcu and channels with
their loads ?

What MCU are you using ? There are processors out there with mux ability out
to 60+......, SAR or DelSig 20 bits....


Regards, Dana.
 
In addition to the schematic…. Your current vs ADC reading vs actual voltage is difficult to follow.

Please make a table as follows: (values below are completely made up but illustrates the nonlinearity.

R value mA. Actual V. ADC read.
0R2 100. 0.02 0.02
0R1 100 0.01 0.01
0R2 200. 0.04 0.034
0R1 100 0.02 0.02
 
Can't provide the schematic but there's nothing else to it, a voltage divider takes the voltage down to voltage ratio and the current is directly over the sense resistor.

The chip is NRF52810 and can't be swapped. It uses SA.

R mA V Adc
0R2 100. 0.02 0.02
0R2 200. 0.04 0.04
0R1 100 0.01 0.012
0R1 200 0.02 0.0242
 
Once the FET source is greater than 0V, the gate-source voltage is being reduced for the "on" device so it's gate-source resistance will increase; the gate threshold can be anything up to 2.5V, so they could turn off completely with source as little as 1.1V above ground.

You would need the gate control voltages to be probably 3V or more above the maximum possible ADC input voltage to ensure the "switch" stayed on.
 
Indeed sir, and the gates are driven at 3.6v and the adc sees a max voltage of 0.4v, though I've not been above a current inducing level of 0.2v so far. Either way, 3.2v which is plenty to make the 2n7002 turn on.

Also, the odd thing is it's voltage over-shoot. With it correct at the resistor and an amplification at the adc pin I'm wondering where it's coming from!

A.
 
May have it. The current is quite far from the nmos and mcu, probably 5cm, and passes on a layer directly under the inductor that generates it. I reckon it could be inducing additional voltage there.
 

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Also, the odd thing is it's voltage over-shoot. With it correct at the resistor and an amplification at the adc pin I'm wondering where it's coming from!

A.
Charge injection, perhaps. A very real troublemaker in simple Mosfet multiplexers.
Do you have on the source side a pull-down resistor? Say 10k.

Depends how fast you are sampling or the bandwidth requirements, but you could also add 10 nF in parallel with the source resistor to absorb the change injection.

Another would be to delay the actual ADC acquisition 100 usec or so from the time you enable the gate.
 
Not sampling it fast at all, 2Hz.

The adc pin has a low pulldown enabled internally, it's something like 10-15k. I tried that to see if it would make a difference.
 

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