Rising edge detector

[Tony Stewart]

still wont work well

https://cscott.net/Projects/FabClass/final/Schematic/edm-power.pdf

read ,, understand then ask questions
https://cscott.net/Projects/FabClass/final/edesign1.html

misc
https://cscott.net/Projects/FabClass/final/Schematic/saviers-email.html

set pulse width, say 50 to 200 us and pulse interval, say 200 us to 2 ms.

Ultra Low ESR Caps are critical for best performance
e.g. not including MOSFET RdsOn
$13 10000µF * 33 mΩ = 330 us " "
$16 10000µF * 18 mΩ = 180 us, " "
$32 10000µF * 8 mΩ = 80 us " "
$37 10000µF * 7 mΩ = 70 us " "

If it just states Ripple current ignore that part.

 

[ronv]

still wont work well

https://cscott.net/Projects/FabClass/final/Schematic/edm-power.pdf

read ,, understand then ask questions
https://cscott.net/Projects/FabClass/final/edesign1.html

misc
https://cscott.net/Projects/FabClass/final/Schematic/saviers-email.html

set pulse width, say 50 to 200 us and pulse interval, say 200 us to 2 ms.

Ultra Low ESR Caps are critical for best performance
e.g. not including MOSFET RdsOn
$13 10000µF * 33 mΩ = 330 us " "
$16 10000µF * 18 mΩ = 180 us, " "
$32 10000µF * 8 mΩ = 80 us " "
$37 10000µF * 7 mΩ = 70 us " "

Hi Tony,
I don't think the first one you posted will work for the reason you stated - It either needs a charge pump or an isolated supply to turn on the FETs.
He has the big power supply caps for a 95 and 130 volt supply as well as pulse caps for the discharge caps. Gap resistance at arc is about 1 ohm.

 

[Tony Stewart]

It appears to have proper Charge pump drivers to me.

Arc Resistance as found by Faraday and finalized by Toepler is;
RT =1.3*10^-5 *d/Q
for d= gap [mm] and Q=C(V2-V1) where V2 is initial and V1 is final

Thus if gap is 0.1 mm max RT =1.3*10^-5 *0.1 * 10 mF*100V = 1.3 uΩ

Ron, is it possible the 1Ω you have seen is surface resistance of part or electrode and rest of circuit?

 

[ronv]

It appears to have proper Charge pump drivers to me.

Arc Resistance as found by Faraday and finalized by Toepler is;
RT =1.3*10^-5 *d/Q
for d= gap [mm] and Q=C(V2-V1) where V2 is initial and V1 is final

Thus if gap is 0.1 mm max RT =1.3*10^-5 *0.1 * 10 mF*100V = 1.3 uΩ

Ron, is it possible the 1Ω you have seen is surface resistance of part or electrode and rest of circuit?

It looks like a bootstrap driver to me, but the resistance in the source of Q2 is 2 meg, so not good for charging the bootstrap cap. I'm not sure I would trust one there anyway.

The gap resistance is total, but the medium is not air, but water or kerosene. So it is not an arc in the traditional sense.

 

[Tony Stewart]

Water has a diectric constant of 60 , kerosene around 4? Plasma with vaporized metal should be very low ESR.

The pump charge resistance is via saturated diode, so will have an ESR ~ 1 watt-ohm , 10 W diode will be ~ 0.1 ohm

 

[ronv]

"Tony Stewart, post: 1219749, member: 214701"]

Water has a diectric constant of 60 , kerocene around 4? Plasma with vaporized metal should be very low ESR.

Most machines have a current limiting resistor. The one you posted uses an inductor to limit the current rise time.

The pump charge resistance is via saturated diode, so will have an ESR ~ 1 watt-ohm , 10 W diode will be ~ 0.1 ohm

What diode?[/quote]

 

[Tony Stewart]

ronv,
the resistance in the source of Q2 is 2 meg, so not good for charging the bootstrap cap. I'm not sure I would trust one there anyway.

Q2 is not a MOSFET it is an IGBT , hence no source pin but rather emitter.
Q2 is used for discharge enable not charging
All IGBTs use gate drivers used cascaded boost voltage gate drivers above this on schematic ( as I recall)

the OP"s plan to use edge trigger without EMI experience is guaranteed to fail with over a million Amp per second rise time near gates.

 

[ronv]

Yes, in your drawing it is an IGBT, in Shortbus' it is a fet. Not that it matters, there is no path to charge the bootstrap cap in the drawing.
But we digress.
Shortbus, I think this is what you are looking for. You would need several, but the idea is the same.
This one starts with charge being on - top trace.
When the cap bank high goes high (2nd trace) it clocks the FF. Bottom trace.
This transfers the high to the Q output creating Discharge. (third trace)
Q not wraps back around and degates the AND gate dropping the clock. (4th trace)

Yes a regular noise machine.

 

[Tony Stewart]

Ronv FWIW my schema ref. uses U6 555 timer to AC couple the pulse with C11 being 1/10th of C12 (V+) then clamped to V+ with D7 and bootstrap pulse fed thru D6 thru jumper pads.

I agree on advice to shortbus, almost like a bounce flash fire, latch ,discharge, light bounce disable circuit.

In this case sensing current power I*t or depth of discharge could regulate constant Joules of discharge unless it is not a fixed R arc.

 

[ronv]

Ronv FWIW my schema ref. uses U6 555 timer to AC couple the pulse with C11 being 1/10th of C12 (V+) then clamped to V+ with D7 and bootstrap pulse fed thru D6 thru jumper pads.

I agree on advice to shortbus, almost like a bounce flash fire, latch ,discharge, light bounce disable circuit.

In this case sensing current power I*t or depth of discharge could regulate constant Joules of discharge unless it is not a fixed R arc.

Ahh yes, I see it now. Do you think he can share one charge pump with the 2 IGBTs?

 

[shortbus=]

Haven't bailed out of this thread . Wife and I are going to classes for home dialysis for her and it is mind numbing. Am working on a better schematic showing what is needed. Thanks for the comments and help.

 

[shortbus=]

Well finally back, life gets in the way sometimes. The attached file is how I envision this working. There are some things missing though, but they are implied and I know they will be needed for it to work. Things like pull up resistors on the comparators, decoupling caps, voltage dividers, etc, etc. But should give the idea of the circuit. Thanks for all the help.

U1, U2, U3 = 4013
U4, U5, U6 = 339
U7 = 4538
inverters = 40106
and gates = 4081

 

[ChrisP58]

It looks like you have the outputs of two, 2-input AND gates tied in parallel. Which is a no-no. If your intent is just to AND 4 signals together, then you should just use a 4-input AND gate.

The CD4082B is a dual, 4-input AND gate.

 

[Reloadron]

You seem to have some pretty high voltages down there on U4 & U5? Looks like 20V and 92V are tied together? What you will need to do is divide the high voltages down to either CMOS or TTL (5V) levels.

Ron

 

[shortbus=]

It looks like you have the outputs of two, 2-input AND gates tied in parallel. Which is a no-no. If your intent is just to AND 4 signals together, then you should just use a 4-input AND gate.

The CD4082B is a dual, 4-input AND gate.

Thanks for commenting. I'm using both and gates separately. Notice that one and pin wraps around to the Q or notQ. This will then allow only one at a time to work with the signal from the corresponding comparator. Doing this makes the 4013/mosfet driver/mosfet combination work together as an "electronic relay" of sorts. Or at least that was my intention. Am I still missing some thing in this? Is there a reason it won't work that way? I am still a noobie at this.

 

[shortbus=]

You seem to have some pretty high voltages down there on U4 & U5? Looks like 20V and 92V are tied together? What you will need to do is divide the high voltages down to either CMOS or TTL (5V) levels.

Ron

Hi Ron, That was one of my "implied" things. Rather than taking the time to show the voltage dividers in this schematic and doing the math for them, I was just showing the "reference" voltage that would be being looked for on the comparators. Both the inputs from the cap bank and the reference voltages on the comparators will be the correct levels on a final "build" schematic. This is I guess what would be a 'proof of concept' drawing, to find major faults in the design. Doing it this way makes it easier for an old learner.

 

[shortbus=]

After looking at the attached schematic this morning I did spot a small mistake. The connection to the "clr" pin on the 4538 timer should go to the same edge detector as the one going to the 'and gate' on the 4538. The 'clr' needs to go low at start up and high during running.

 

[Tony Stewart]

Lots of logic complexity and chances for errors, race conditions, EMI false triggers etc. burnt out CMOS SCR effects etc.


Start with block diagram with ins and outs with functions and timing diagrams including impedances for in and out. eg Rg, RdsOn Imax, Pmax, ESR on Caps and ESL for layout.

Then consider EMI protection from arc noise.

Then choose best topology for timing and drivers.

Too soon to start implementation specific choices with logic.

We call it a Design Spec.

 

[shortbus=]

Tony, the questions you are asking me are way over my level of knowledge. This type of circuit has be done by others with a lot less than you saying, and they are working. I don't see how there can be any 'race' conditions in the logic. One step has to be completed before the next is even possible to happen. This is not nor will it be for a commercial machine, it is for home workshop use. As in my reply to Reloadron, this is not a finished/build schematic, and I know things that are missing will have to be added and will be if the "basics" of the design are judged feasible by members.

The logic is not clock driven, and can't be made to work with a frequency driven clock. It is dependent on voltage levels rising and falling in the different sections of the circuit. The circuits that are frequency driven all suffer from the same problem, missed sparks/pulses. This is why I am trying to use a circuit that only advances to the next step when the conitions of the previous step are met.

 

[ChrisP58]

You may need two separate AND functions, but you still cannot just tie the two outputs together unless both outputs will always be in the same state. If the two outputs are different then they will fight each other. At best, the voltage of the two mismatched states will be half the operating voltage. What you will not get is the clean rising edge into the clock pin of your flipflops.

If you need to tie the outputs of the two gates together, you need another gate to do it. If you need to OR them, a CD4001 is a quad, 2-input OR Gate. There may be other options depending on what you really need to do.