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Problem with counter

Thread starter #1
I need to make mod-12 asynchronous down counter using T flip flop. It counts from 15 to 4. I don't know really how to do it and it's really important, so if you could help me i would be very grateful!
Thanks! :)
 

MikeMl

Well-Known Member
Most Helpful Member
#4
Look up "Modulo" in mathematics.

You are trying to build a counter that has exactly 12 states. Those 12 unique states can be named anything, including 15,14,12,...,5,4. When you build a counter out of "state elements" (flip-flops), you can arrange them in many ways. You should strive to arrange them so that the numerical value of the states as defined by the binary pattern of the individual flip-flops matches the numerical value such as 15=1111, 14=1110, ..., 0101=5, 0100=4.

With this in mind, you should be able to create a "present state - next state" table.

Question for you: How many flip-flops does it take to represent 12 unique states?
 

ci139

Active Member
#5
for your inconvenience this can be done in multiple ways (i'm a lazy cat so trying to spot existing course materials from the inet)
primary search: https://www.google.ee/search?client=firefox-b&dcr=0&biw=1280&bih=915&q=cmos+u/d+synchronous+binary+counter+explained&oq=cmos+u/d+synchronous+binary+counter+explained&gs_l=psy-ab.3...7765.29262.0.30150.35.35.0.0.0.0.228.3870.12j20j2.34.0.dummy_maps_web_fallback...0...1.1.64.psy-ab..1.5.600...0i7i30i19k1j0i7i10i30i19k1j0i19k1j0i5i30i19k1.0.8JZ6GoWxC50
reveals
 
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MikeMl

Well-Known Member
Most Helpful Member
#7
I think 4 flip flips.
Correct 2^4=16, so 4 flip-flops can represent 16 different, unique states. Only 12 of the 16 are useful to you. What happens to your counter if it accidentally gets into one of the 4 unused states?

Can i send you truth table so you could tell me is it right?
Sure. You make your best effort. Post it here, and then we will comment on it. That way, you learn something...
 

MikeMl

Well-Known Member
Most Helpful Member
#9
ci139 I know you want to be helpful, but in the homework forum, we usually do not just hand out a solution. We try to make sure the student learns something in the process...
 

ci139

Active Member
#10
just hand out a solution
i agree . . . but is it a solution ? . . . i barely got it work coz the maladies of a simplistic simulator
+ in case it verifies to a solution - ? is it optimum or what there should be (as expected by course master ?)
it initalizes "right" only by pure chance (by the specifics of the simulator)

. . . it is not a solution but rather a warning what everything might go wrong while attempting to find one
 

ci139

Active Member
#12
i solved your case for async. J-K , async T , synchronous JK and sync T -- for the least two with auto-break-out from couter state below 4

my map for the synchronous versions ?
15to4dnct.png
 

ci139

Active Member
#13
ok, you list the [output states to][output states from] whitch is an alternate to https://en.wikipedia.org/wiki/Digital_timing_diagram
basically you can use either or both what you find more convenient

when it comes to a dynamic circuit elements such as triggers the output of such is not a fixed 1 to 1 accordance but also it's internal state
this may complicate keeping track on events and to design your sys - so far you've done all actually correct (not getting lost in the time sequence)

also right is that you have defined the output as the function of input

you haven't told us not shown the particular T-flops you have to implement this function on
? synchronous (with the C (clock) input) async. (T input only) -- the function you try to achieve depends on that

Hi, my name is Justin Case
T-flop time offset
 
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MikeMl

Well-Known Member
Most Helpful Member
#14
If the counter is in Present State 14, what is the Next State? (Not what you show! You show 15, but it should be 13. I don't understand what you put in the "Next State" columns.)

If the counter gets into state 3 accidentally, what state does it go to next? You need to account for those "unexpected states" , too.

states.png
 
Thread starter #15
upload_2017-10-4_15-4-7.png
Ok, so this is the table of a down counter. But i need a MOD 12 down counter, so after stage 4 i need to go back to stage 15, like this

upload_2017-10-4_15-11-28.png
But state 3, 2, 1 and 0 are unwanted so i think i need to fill up those gray fields with "X", and then when i do K-map i could see at what place "X" will be replaced with 1.
 

MikeMl

Well-Known Member
Most Helpful Member
#16
There are many different ways to treat states 3 to 0. If you use them as don't cares "X" in the state table, it might simplify the gating required to implement the counter, but then you really need to test for "hazards" after you are done.

I once designed a counter that went into a commercial product where I created a hazard short loop. Occasionally, on power-up, the flip-flops would come up in one of the "dont-care" states, but the hazard was that the counter had two stable counting patterns; the desired one and the undesired shorter one. You need to verify that the next state for states 3 to 0 lead to one of the "legal" states. My boss was not happy...
 

ci139

Active Member
#17
there are 5+ ways to achieve this
  1. the syncronous *by "boolean expressions"
    • as the input T-high allows "count" (output swap) and the T-low disables it
      you set your T by previous output of all Qx -s using boolean arithmetic operations (implemented on digital circuitry)
      the breakout from undesired loops is achieved by setting up an additional control to some of the Tx -s
      (which is activated when the triggers output is at undesired range) - versus - you initialize your triggers to a
      "legal" output (again by setting up initialization cycle or synchronously driving the Reset Set inputs if they are implemented)
  2. the synchronous by additional memory-/RAM-/EEPROM lookup-table
    • potentially the fastest (depending on memory type)
      the same as above but your digital T-driver functions is stored statically in RAM/ROM adressed by "counter output"
  3. the async. by logic circuitry - where each prev (trigger/couter stage →) Qx defines* the next Qx+1
    (there will be time delay before MSB-s set by/after LSB-s do)
    • has a perhaps a more complex implementation than the ones above <not described here - if you can do above then you can figure out and this>
  4. the async./to sync. counter -- by setting T→ input aside as an async. clock →C
    and implementing syncrounous inputs for that new "clock" as in "1."
  5. (sh¡t - i don't remember already) . . .
  6. if avail than using RS inputs to handle "**non-trivial" state transition
    by disabling/+redirecting the T-/clock- (see. "4.") input for such** transition
    and precisely driving RS inputs to achieve desired output state ...
  7. as in "2." - implementing the entire thing on ROM
    https://www.ibiblio.org/kuphaldt/electricCircuits/Digital/DIGI_16.html
    https://www.ibiblio.org/kuphaldt/electricCircuits/Digital/DIGI_11.html
 
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Colin

Active Member
#18
All this requirement has died 10 years ago.
Counters use a microcontroller and this allows up and down counting, false triggering, setting a count, creating an alarm, and lots of other features with a single chip costing 50 cents! Look at what the Chinese have !!!!! STC15W201S
 

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