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LTspice hierarchical block

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Hi

I am using LTspice to create a hierarchical block for a custom circuit. I keep getting the error

upload_2018-6-12_7-24-15.png

I tried debugging the problem and everything in the symbol seems correct. The symbol is associated with my schematic.

upload_2018-6-12_7-27-7.png

I also viewed the symbols netlist and got the error

upload_2018-6-12_7-28-13.png

I am not sure what I am doing wrong. I would appreciate any help.

Thanks
 

DerStrom8

Super Moderator
Most Helpful Member
Your out1-out5 connections appear to not be connected. Note the electrical connection point on the left-hand side. There are no wires connecting to them.
 

eTech

Active Member
DerStrom8 is right.

You have the "out" labels at the left of the schematic disconnected. Mirror them so they will connected to the wires.

Also...
Remove "Memory" from the symbol "value" field until the schematic is converted to a .subckt file containing a "Memory" subckt definition.

eT
 
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