LM311+ 74HC74 FLIP FLOP - BAD DESIGN?

[MacIntoshCZ]

Hello,
I am having trouble with my design. Its not working. LM311 is switching fine but i got just tiny pulse as response at Q 74hc74 output. When i apply signal (square wave) directly to flip flop it changes state. Using FY6900 as signal generator.
Do i missed something? LM311 Low logic VOLT is 0,25V , LO on 74hc74 is higher (up 1-2V i guess).

 

[MacIntoshCZ]

BTW thanks for help

 

[crutschow]

Check the clock risetime requirements for the 74HC74.
It's maximum at 5V is about 0.7us.
Is the LM311 output at least that fast?

A CD4013 is a slower device and may work better in your circuit.

 

[MacIntoshCZ]

Sorry i dont understand what are requirments for rise time? It will not change state when rise time is higher than 0,7us? i though it just compare voltage - it needs value under LowLevel and value above HighLevel.

 

[MacIntoshCZ]

So it looks it has long rise time. 810nS

 

[picbits]

I've had issues before with oscillation on the transition on comparators. Make sure you have proper decoupling near the power pins, no earth loops etc and maybe put some hysteresis

 

[Diver300]

Sorry i dont understand what are requirments for rise time? It will not change state when rise time is higher than 0,7us? i though it just compare voltage - it needs value under LowLevel and value above HighLevel.

The problem is that the input can spend too much time at a voltage level where the slightest bit of noise can cause the output state to change again. That noise can come from the output changing, so you can get the flip flop oscillating.

The LM311 isn't particularly quick so it might be too slow for the 74HC74. The specification that I found for the 74HC74 is 139 ns/V maximum, so 810 ns is a bit too slow.

You could try a smaller pull-up resistor, or you could try some positive feedbac.k from the output to the +ve input. You might need a resistor in series so that the feedback resistor has an effect.

 

[rjenkinsgb]

Someone else on here (I can't remember who) has used an ingenious self-debouncing design before now;
just connect a resistor-capacitor delay between /Q out and D in.

As long as the new D value is stable before the next wanted clock transition, any noise or multiple transitions on the clock line will be ignored as the D will not change for a short time.

eg. try 10K series and 1nF from D to GND if it's only working at audio frequencies.

 

[crutschow]

It will not change state when rise time is higher than 0,7us? i though it just compare voltage - it needs value under LowLevel and value above HighLevel.

And why did you think that?
The FF triggers at a certain voltage level but it is edge-triggered not just level-triggered, and needs a minimum risetime for proper operation.
When all else fails, look at the data sheet.

 

[schmitt trigger]

Most likely oscillations during the transition, you should add hysteresis to the comparator.

The LM311 datasheet is very comprehensive with respect to other probable sources of spurious oscillations.

 

[MacIntoshCZ]

And why did you think that?
The FF triggers at a certain voltage level but it is edge-triggered not just level-triggered, and needs a minimum risetime for proper operation.
When all else fails, look at the data sheet.

Cause i am an amateur .
I just played a little bit with exponencial function on dds generator . Yeah it start works when rise time is under 220ns.
So my design was stupid.
Thanks for help.

 

[MacIntoshCZ]