Instantiating Into Top Module Verilog

[wuchy143]

Hi,

I have two modules(two different .v files) and would like to put them together to form one module which I can test. Does anyone know how I would do this? I'm pretty sure I need to instantiate my two lower modules into my top?

-mike

 

[wuchy143]

I took a stab at the top1.v to instantiate my decoder.v and waveform_gen.v. Xilinx ISE give me and error which isn't very helpfull.

"ERROR: Failed to create the command line for XST. One or more procedures reported errors."

Does anyone have an idea of where I'm making my error. It all is making sense to me. PLEASE HELP!!!

module top1(
port_sw, //input switch to select note
port_audl, //output tone to speaker
port_50clk, //input clk from 50MHz oscillator
port_reset //reset AUD_L to zero
);

//input output top1
input [3:0] port_sw;
output port_audl;
input port_50clk;
input port_reset;

//internal hookup
wire COUNT_VAL1;

//instantiate decoder
decoder decoder_inst
(
.port_sw(SW),
.port_50clk(CLK_50M),
.COUNT_VAL1(COUNT_VAL)
);

//instantiate waveform_gen
waveform_gen waveform_gen_inst1
(
.port_50clk(CLK_50M),
.COUNT_VAL1(COUNT_VAL),
.port_aud1(AUD_L),
.port_reset(reset_n)
);

endmodule