im looking for a simple 8 bit dram refresh circuit

[777xxx]

i have some 4164 dram chips and i want to build a refresh circuit for them. ive tried looking on google but cant seem to find anything understandable. any help would be appreciated.

 

[Nigel Goodwin]

Is there any point these days?, you can buy cheap static rams which are far easier to use, 32K ones in 28 pin packages are cheap and common.

 

[777xxx]

Is there any point these days?, you can buy cheap static rams which are far easier to use, 32K ones in 28 pin packages are cheap and common.

i have some that i want to use up

 

[Nigel Goodwin]

i have some that i want to use up

It's just more time and money wasted, and a poorer result.

You might try looking up the Apple II which uses 4164's and hardware refresh, and there's plenty of information about it.

 

[rjenkinsgb]

You use an 8 bit counter gated to the address pins, pulse /RAS low at regular intervals between normal access cycles. It needs to cycle through all 256 addresses every 4mS or less.

 

[rjenkinsgb]

ps.
Lower cost: 256KB or 512KB in single ICs with trivial cost:

https://www.mouser.co.uk/ProductDetail/Alliance-Memory/AS6C1008-55PCN

https://www.mouser.co.uk/ProductDetail/Alliance-Memory/AS6C4008-55PCN

 

[danadak]

@OP, I resurrected 1103's some years back mainly as a challenge due to the complex seriously ugly timing.

Quite instructive an a great rainy day activity. I have some 2900 bit slice and Signetics
8X300 parts I want to tackle at some point as well.

Good luck with your effort.

 

[777xxx]

ps.
Lower cost: 256KB or 512KB in single ICs with trivial cost:

https://www.mouser.co.uk/ProductDetail/Alliance-Memory/AS6C1008-55PCN

https://www.mouser.co.uk/ProductDetail/Alliance-Memory/AS6C4008-55PCN

links dont work

 

[rjenkinsgb]

Sorry;

https://www.mouser.co.uk/ProductDetail/Alliance-Memory/AS6C1008-55PCN?qs=E5c5%252Bmu3i39qb4Qta5D2qg%3D%3D

https://www.mouser.co.uk/ProductDetail/Alliance-Memory/AS6C4008-55PCN?qs=E5c5%252Bmu3i3%252BMOyro1Tlhzg%3D%3D

 

[ronsimpson]

Years ago, I had the CPU refresh every 1mS. Set up an interrupt for the timing. I think I did 256 sequential reads as fast as possible. Don't remember the details.

 

[rjenkinsgb]

The only ones I've built myself were for an old MC6809 system.

That CPU uses quadrature clocks (E & Q) and only access memory during E high.
I use E low & rising edge of Q to trigger a refresh then increment the counter.

(I had 1MB of dynamic RAM on that system).

 

[Ian Rogers]

The RAS just needs a signal every 2mS Look at this

Arduino and 4116 DRAM

Just to play, but you'll get the idea.

 

[rjenkinsgb]

The RAS just needs a signal every 2mS Look at this

The refresh cycle time is the maximum spec within which all row addresses need to be refreshed.
(And different makes of the same device type can have different limits - this is a Mostek one, 2mS rather than 4mS).

REFRESH
Refresh of the dynamic cell matrix is accomplished
by performing a memory cycle at each of the 128
row addresses within each 2 millisecond time interval.

 

[atferrari]

Not sure if it is actually what you are looking for but the technical manual of the ZX81 or Timex Sinclair, had its refresh circuit explained.