i have some 4164 dram chips and i want to build a refresh circuit for them. ive tried looking on google but cant seem to find anything understandable. any help would be appreciated.
You use an 8 bit counter gated to the address pins, pulse /RAS low at regular intervals between normal access cycles. It needs to cycle through all 256 addresses every 4mS or less.
Years ago, I had the CPU refresh every 1mS. Set up an interrupt for the timing. I think I did 256 sequential reads as fast as possible. Don't remember the details.
The only ones I've built myself were for an old MC6809 system.
That CPU uses quadrature clocks (E & Q) and only access memory during E high.
I use E low & rising edge of Q to trigger a refresh then increment the counter.
The refresh cycle time is the maximum spec within which all row addresses need to be refreshed.
(And different makes of the same device type can have different limits - this is a Mostek one, 2mS rather than 4mS).
REFRESH
Refresh of the dynamic cell matrix is accomplished
by performing a memory cycle at each of the 128
row addresses within each 2 millisecond time interval.
The Apple II+ used 4116 DRAMs, other Apple II models used 4164 or denser DRAMS, with the same refresh rate.
Tandy's TRS-80 Model 1 used the buffered /MREQ line to refresh 4116 DRAMS on its mainboard and Expansion Interface, but its chips were directly soldered to the PCB to prevent unauthorized/ incorrect removal.