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Designing Schmitt trigger oscillator using CMOS NAND gate.


New Member
I am designing a Schmitt trigger oscillator based on a CMOS NAND gate. The block diagram along with schematics and its results are attached for your reference. I am using the CADENCE tool with 0.35um technology.

Question: it can be seen in the result, the charging time of the capacitor is large which affects the oscillating signal at the beginning. To reduce charging time I need to reduce the RC time constant but it affects my oscillating frequency. Once i reduce the RC time constant then i am limited to a certain oscillating frequency.

Oscillating frequency: f=1/2.2RC

How can I reduce the charging time of the cap (other than the RC time constant in my schematics) so that I get the least distortion at the initial stage of the oscillating signal?


schmitt trigger

Well-Known Member
The enable signal has to go to the second gate.
Have the first gate running continuously to ensure that when the enable signal is asserted, you immediately get a pulse train.


Well-Known Member
Precharge "C" before enabling the OSC.
You'll need to tweak the divider values.

Last edited:

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