Large C connected to CMOS Inputs

[danadak]

Folks seem to like building delays, debounce keys, etc, by placing large C at the
inputs to CMOS gates.

NOT A GOOD IDEA

For case where supply collapse rapid due to its design, load situation.

TI confirms this in an ap note on general CMOS usage. Here is a rough sim of the problem.
Note since spice model did not have the parasitic diodes in it I used external as substitute.
Also used 1 ohm as C ESR......roll your own value(s) for your case. Note using .1 ohms for
C ESR produced 3A thru D1......

The simple way around this is to place a series R between gate input and the large C.


Regards, Dana.

 

[danadak]

eTech, Model had its I/O pins reversed. Here is sim (100 mV RMS noise) :

By the way try out free version of Simetrix simulator. Used to be Analog Devices
mainstream until they bought LTC and decided (in error I think) to standardize
on LTC spice. There are videos.


Regards, Dana.

 

[eTech]

eTech, Model had its I/O pins reversed. Here is sim (100 mV RMS noise) :

View attachment 145000


By the way try out free version of Simetrix simulator. Used to be Analog Devices
mainstream until they bought LTC and decided (in error I think) to standardize
on LTC spice. There are videos.


Regards, Dana.

I'm curious as to why the noise generator for this test?

 

[danadak]

If you look with your scope you will see noise on your supply rail and ground bounce
noise, both always present in various levels. Set your scope on infinite persistence,
always eye revealing.

When I put my scope on almost any supply feeding processors and clocked logic I always
see ~ 100 - 200 mV noise, scope set on infinite persistence to capture pk-pk noise.


Regards, Dana.

 

[eTech]

If you look with your scope you will see noise on your supply rail and ground bounce
noise, both always present in various levels. Set your scope on infinite persistence,
always eye revealing.

When I put my scope on almost any supply feeding processors and clocked logic I always
see ~ 100 - 200 mV noise, scope set on infinite persistence to capture pk-pk noise.


Regards, Dana.

Even with decouping and PS filter caps?

 

[danadak]

Depends on board, supply, cap quality, numbers of, PCB layout, amount
of active clocking devices and peripherals running, loads, a myriad of variability.

Here is a fairly well laid out board (its a PSOC 5LP board) which has a 20 bit
A/D on it, controlled Z board.

I ran the system longer after above screenshot, ~ 180 mV of noise. Note < 20% of onchip
resources active, so makes one wonder what it is running all peripherals. When using hi
res A/Ds such as the one inside frequent recommendations is to stop running peripherals to take
a sample, for obvious reasons.

ignore the big transient in middle of screen, not sure what caused that. Vibration on bench
and probe mechanical contact might have done that.


Regards, Dana.

 

[Tony Stewart]

Thanks.

Can you try the same using an unbuffered inverter 74HCU04?
If not, Ok. Just curious about the results.

Why do you need this? AFAIR each inverter has a wide tolerance in thresholds around 1.5V with Beta around 20m. As I recall, I expected each 4000 series stage to have at least a gain of 10 , thus a buffered inverter was >= 1000 also with a wide GBW with temp and Vdd voltage. Relaxation oscillators could easily be made with 3 buffered or non-buffered inverters or used as linear amplifiers with NFB in the 4xxx series, but not so easy in the 74HCxx series as they are not unity gain stable due to <50 Ohm Rout. Decoupling Cap ESR is also important to avoid PSRR issues.

If your cap has an ESR of 1 to 5 ohms with a 33 Ohm transition with 10 pF load, how much is your noise suppressed?

 

[eTech]

Why do you need this? AFAIR each inverter has a wide tolerance in thresholds around 1.5V with Beta around 20m. As I recall, I expected each 4000 series stage to have at least a gain of 10 , thus a buffered inverter was >= 1000 also with a wide GBW with temp and Vdd voltage. Relaxation oscillators could easily be made with 3 buffered or non-buffered inverters or used as linear amplifiers with NFB in the 4xxx series, but not so easy in the 74HCxx series as they are not unity gain stable due to <50 Ohm Rout. Decoupling Cap ESR is also important to avoid PSRR issues.

If your cap has an ESR of 1 to 5 ohms with a 33 Ohm transition with 10 pF load, how much is your noise suppressed?

I'm aware of that.
I wanted to see the simulation results and gave Danadak the option of ignoring my request.
Danadak was nice enough to provide it.