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cmos circuit

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Q1) how can we reduce power dissipation in cmos circuit?

Q2)why nmos and pmos have different W/L ratio
to obtain the same raise time and fall time in cmos circuit , the w/l ratio of Pmos should be double then nmos
 
what should we do to achieve specific delay
just example for my understanding ( 215 ps)

I think I need following thing but its not all I am missing some
1.power supply
2.threshold voltage for nmos
3.threshold voltage for pmos
4.load capacitance

please anyone tell me what should we do to achieve 215 ps delay
 
You are trying to design a Cmos IC but nobody on this forum has ever done that.
You need to ask an engineer who has done that or ask your teacher.
 
You are trying to design a Cmos IC but nobody on this forum has ever done that.
You need to ask an engineer who has done that or ask your teacher.
I don't know any experience design engineer. I just wanted to know method I mean I have decided specification and i wanted to start next step but ok thanks for giving valuable response
 
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I am an experienced design engineer but I have never designed an integrated circuit and I do not know an engineer who designs them.
 
You said you are doing some kind of online course or something. I bet they have some material for you to study before you do the test.
Or, you might try going to school.
 
Most of us learned electronics in University. When I went to University 50 years ago they did not teach how to design a Cmos integrated circuit but maybe they teach it today.
 
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