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cmos circuit

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Parth86

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I need some query about cmos circuit

cmos circuit specification
Input voltage
output voltage
input current
output current
transistor width
transistor length
fall time
raise time

now my main problem is how do decide specification for circuit

1)Input voltage - It can be 3.3 v or 5v If its 3.3 volt then what will be output voltage ?

I think input voltage depend on output voltage and output voltage depend on input voltage that means If we know input voltage we can determine output voltage and as same for output voltage

2)how to choose transistor size for low power consumption ?
transistor size effect raise time and fall time

what will be transistor size for 100 200 300 ns ?

as rule one is known then we can determine unknown value so I am trying do this method
 
An electronic circuit has a function. You do not know and we do not know the function of the circuit you want to design.
Is the circuit linear or logic?
Why don't you simply buy a Cmos IC that is already designed to do whatever you want it to do?
 
I think input voltage depend on output voltage and output voltage depend on input voltage that means If we know input voltage we can determine output voltage and as same for output voltage
I believe the input and output voltages are mostly based on the supply voltage. The current is mostly dependent on the load.

you could also say the input voltage depends on the input (sensor) and the output voltage is determined by the output (load).

It all kind of goes hand in hand.

Does this help?
 
An electronic circuit has a function. You do not know and we do not know the function of the circuit you want to design.
Is the circuit linear or logic?
Why don't you simply buy a Cmos IC that is already designed to do whatever you want it to do?
I am reading about cmos circuit, I wonder how designer think when they design new chip

- they determine the requirement of customer
answer- less delay, low power consumption, low voltage

- then they decide specification ( i made temporary specification)
Input voltage 3.3 v
output voltage 3.0 v
input current 1.5 micro amp
output current 1.0 micro amp
transistor width 6 micron
transistor length 2 micron
fall time 2 ns
raise time 3 ns

I agree with 4pyros
one value depend on another value
if load is greater then less current will be flow
if power increase raise time will increase so we need less power

how they decide specification
I mean how they make chip that work fine
I just want to know how does designer think ,
 
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You do not understand what the word "function" means in English.
Is the new chip a linear amplifier? Is it a linear radio circuit? Is it a digital time clock? Is it a digital microprocessor? These are functions.

You say an input current of 1.5 micro amps. But don't you know that Cmos has NO input current (only a very small amount of leakage current)?
 
You do not understand what the word "function" means in English.
Is the new chip a linear amplifier? Is it a linear radio circuit? Is it a digital time clock? Is it a digital microprocessor? These are functions.

You say an input current of 1.5 micro amps. But don't you know that Cmos has NO input current (only a very small amount of leakage current)?
I am not talking about specific one for example you can suppose cmos inverter

And I am trying to improve my English
 
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Are you talking about a simple Cmos logic inverter (A CD4069 uses only two Mosfets for each of its six inverters) or a complicated DC to AC power inverter?
 
The CD4069 Cmos hex logic inverter IC has been available since 1968 (46 years). Like most of the other CD4xxx logic ICs its supply voltage (not its input voltage) is from 3V to 18V and its datasheet shows that it switches fairly slowly and has low output current but uses almost no supply current when it is switching fairly slowly.

The 74HC04 Cmos hex logic inverter came later and its supply voltage is from 2V to 6V. It switches fairly fast with a higher output current and it also uses almost no supply current when it is switching slowly.

Their power dissipation increases when they are switching fast because their output must use current to charge and discharge capacitance.
All their spec's (but not the width and length of the transistors) are shown on their datasheets.
 
AND gate cmos transistor sizing

AND gate with cmos transistor
we can create cmos AND gate with 3 nmos and 3 pmos transistor

Equation X=AB

AND gate cmos circuit= <-NAND--Inverter->

I want to size the transistor so that the output resistance is same as that of inverter with nmos W/L=3/2 and pmos W/L=6/2

inverter with nmos W/L=3/2 and pmos W/L=6/2

parallel pmos (L will double with same W)

pmos 1 W/L=6/4 and pmos 2 W/L = 6/4

nmos series ( W will double with same L)

nmos 1 W/L= 3/4 and nmos 2 W/L=3/4
transistor size for AND gate cmos

nmos 1 W/L=6/4
nmos 2 W/L=6/4
nmos 3 W/L=3/2


pmos 1 W/L=3/4
pmos 2 W/L=3/4
pmos 3 W/L=3/2

IS this correct sizing for AND gate
 
look at this Image
how to do transistor sizing for this Image
1)can we keep same size ?
2) when we size transistor what should we know?
 

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This must be school work. Most of us are not still in school trying to design an IC that is 46 years old, instead we simply buy them and use them in circuits that we design.

The old CD4081 has 2 more stages of inverters that your circuit does not have and it also has a protection circuit on each input that is missing on yours.
 

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ok I will do myself but I have some doubt

1)why the ratio W/L is important in cmos circuit
2)why nmos and pmos transistor at inverter have different W/L ratio (nmos W/L=3/2, pmos W/L=6/2)
 
ok I will do myself but I have some doubt

1)why the ratio W/L is important in cmos circuit
2)why nmos and pmos transistor at inverter have different W/L ratio (nmos W/L=3/2, pmos W/L=6/2)
You should ask an engineer who designed these old ICs, ask your teacher, look in your text book or look in Google.
 
I am student ,I am not Ic designer i have done this work

when designer design new circuit, they think whats the requirement

step I
1)power dissipation should be less
2)raise time and fall time should be less
3)propagation delay time should be less
4)size should be small as possible

step II

1) how can we reduce power dissipation in cmos circuit?

- we have to decrease voltage or current in circuit
- we have to decrease resistance in circuit

2) how can we reduce raise time and fall time?
-which parameter depend on raise and fall time
 
how can we reduce raise time and fall time?
-which parameter depend on raise and fall time
What slows down the rise time and fall time of a waveform? CAPACITANCE!
How can you reduce the capacitance? A small low power Mosfet has less capacitance that a large high power Mosfet but the capacitance is charged and discharged quicker when the current is higher which needs a higher power larger Mosfet. Then you must compromise them.
 
If load is greater then less current will flow so IF we increase load then current will be increase
A load cannot be greater and it cannot be increased.

Instead the resistance of a loadcan be greater or the resistance of a load can be increased or decreased.

A Cmos logic IC usually drives the input of another Cmos logic IC that has no input resistance so the resistance cannot be changed. The capacitance of the Mosfets and stray capacitance are the load.
 
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