Circuit for edge delay, signal on timeout

[tim__]

Hi,

please help me with my design problem

Problem part1
I need a circuit which delays the rising edge of a TTL signal by lets say 7 microseconds. There is no constraint on the falling edge's delay, so it may also be delayed by the same amount of time.

Problem part2
I need a circuit which generates an interrupt whenever the TTL signal of part1 stays at the low level for at least 60 microseconds after the falling edge. This is a sort of timeout generation. The interrupt is either a falling or rising edge, whicever is easier to implement.

I must do the realization with a minimum component count on the same board. I have 3/4 spare 74HC125 gates. Moreover I have a spare comparator in the CMOS microcontroller with the input pins available. I must perform these functions in hardware. The delay must not vary significantly throughout temperature change or component tolerance. (Tolerance is a few microseconds.)

Any help would be greatly appreciated.

 

[Optikon]

Hi,

please help me with my design problem

Problem part1
I need a circuit which delays the rising edge of a TTL signal by lets say 7 microseconds. There is no constraint on the falling edge's delay, so it may also be delayed by the same amount of time.

Problem part2
I need a circuit which generates an interrupt whenever the TTL signal of part1 stays at the low level for at least 60 microseconds after the falling edge. This is a sort of timeout generation. The interrupt is either a falling or rising edge, whicever is easier to implement.

I must do the realization with a minimum component count on the same board. I have 3/4 spare 74HC125 gates. Moreover I have a spare comparator in the CMOS microcontroller with the input pins available. I must perform these functions in hardware. The delay must not vary significantly throughout temperature change or component tolerance. (Tolerance is a few microseconds.)

Any help would be greatly appreciated.

Guidance on part 1:

Consider RC delays and Cmos buffers. It will delay both edges but thats OK. Use metal film low tempco and ceramic or polyxx cap, temp drift should be a problem. You'll likely have to tweak the resistor to get sufficiently close to 7us delay as you wont precisely know where the gate thresholds are.

Guidance part 2:

Consider a monostable (i.e. a one shot). A rising edge can trigger another RC delay and after delay passes, it will return to original level. You will need some logic on the triggering (falling edge) and some logic to determine if the signal remains low after the monostable has returned (timed out). Of course if the signal returns high before the monostable times out you should reset it or disable it somehow.

Alternatively, can you provide a clock from the uC ans use a counter to count 60 microseconds? You can then devise a similar scheme.

For minimum component count, use uc as much as possible since its there anyways. Also you can get monostables and logic with multiple parts per package. RC delays are low cost but require more parts (small though)

Put together a sketch of your idea and post it for further guidance.