OK. First, let's look at your schematic and how it operates (from what I can see), and you tell me where I'm wrong. Then I'll explain (after you respond), what it is I need to do.
The J-K flip flop's "preset & clear" functions are asynchronous meaning they happen immediately. They do not wait for any signal or gates to change. They do it instantaneously.
I am aware of this. The J-K's reset only takes place when it goes low, hence the term "toggle" (it automatically cycles <from low to high, or from high to low> with
EACH clock input at the clock input's low-to-high transition). Your circuit keeps the J-K's reset high at
ALL times, so your J-K does this toggling of the outputs on each clock's low-to-high. But this means if the J-K is already high, it will stay high until the next clock transition (from low to high), and vice-versa. The clock signal is your gate sampler (duration of incoming signal sampling). Your J-K endlessly oscillates it's output, going high every OTHER low to high output of the clock signal. I am also aware that the J-K is used to generate a square wave signal to filter the clock signal. If the clock is coming in at 100Hz (divided), then the J-K's square wave goes high for .01 secs and then low for .01 secs (50/50), because it toggles ONLY on EACH low-to high transition, and each of these transitions changes the output state of the J-K to the opposite of what it currently is.
The following "textual flowchart" is w/ use of the divider (100Hz), and the J-K's output is high...
The Qd outputs a clock (low->high) transition, so the J-K's output now goes low and then...
1.) The AND severs the signal which allowed the sampled signal to be routed to the counters. The transistor delay circuit will start charging. The L/D/D remembers the most recent BCD from the counters (due to LD <latch disable> now being low), because that BCD was read through the L/D/D's last high. The BL (blanking) is lifted (now low), and the display shows the L/D/D current stored count.
2.) The transistor delay thresholds / sends a high signal to reset the counters. The purpose of delay is to allow time for BCD to be loaded to the L/D/D before the counters are reset.
3.) Your divider does not reset, because MR (pin 14) is always low (but the counters DO reset <via pins 2 & 14> because they are controlled by the transistor delay). Therefore, you will always have a value between 0 and 9 within your divider, no matter what state the J-K is in, because that divider is tied directly to your clock signal and MR is always low.
4.) The sampled value is displayed for the .01 second duration that the J-K remains low.
The next clock (low->high) transition arrives, the J-K's output goes high and then...
1.) The AND starts allowing the sampled signal to be counted. The BL (blanking) will be enabled (now high) and the display will not show any value.
2.) The sampled value is tallied by the counters.
3.) The L/D/D "tracks" the changing BCD (LD is high), for storing when it's LD goes low.
4.) Your divider's Qd stays low and eventually goes high (at some point), but not necessarily every 10 cycles (re CL always tied to the clock signal and MR <pin 14> always being low), because it never gets reset. This plays little factor in your circuit because your utilizing the circuit to count millions of cycles, and the divider would at a maximum, yield little variation, because your also sampling it at a very high rate (100Hz, every <other> .01 seconds).
5.) When the divider Qd goes high again (after .01 seconds <or so>), the cycle starts over.