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The switch merely changes the resolution of the last digit to either 1KHz or 100Hz. The numbers shift left one digit position so yes if you want to read down to 1Hz resolution you must add parts. If you want LED then you will need different drivers than the 4543's. Look around. They should have something compatible except with LED drive instead of this LCD drive. Another route you could take is to order LCD display with "transflective" variety where you can add a back light. They have onen that distribute the light very evenly and goes directly behind the transflective LCD.
If I want to read down to 9999.9Hz, how would I alter this circuit? Is it "impossible" to get this circuit to display the last digit as a tenth??
I figured just a different driver for the LED display, but I was also wondering if I would need to add other parts to possible support the current. How about 74LS47s from the 74LS390s? Or maybe this circuit (4543) and use low current Darlington Drivers (CMOS compatible L604)?
As your circuit stands, what is the maximum VCC? (15v??)
If I want to read down to 9999.9Hz, how would I alter this circuit? Is it "impossible" to get this circuit to display the last digit as a tenth??
I figured just a different driver for the LED display, but I was also wondering if I would need to add other parts to possible support the current. How about 74LS47s from the 74LS390s? Or maybe this circuit (4543) and use low current Darlington Drivers (CMOS compatible L604)?
As your circuit stands, what is the maximum VCC? (15v??)
VCC is just 5 volts. If you want the circuit to dived down further you need more decade counters and of course more display drivers. The way it works is, as long as the frequency you are feeding into the circuit is able to to be counted by the speed of the counters you are fine. So let's assume you never put any frequency into it higher than say 40MHz. Now, why does it not count further than 1000 and 100Hz? Because the first counter counts the overall megahertz then passes along a remainder to the next decade counter which becomes the next digit place and so on. So if you want to read down to 1Hz or .1Hz as you stated, then you want to simply continue the string of decade counters the same way as they are done on the previous counting stages. You will use the Qd output of the last counter (before the J-K flip flop) and run it to the clock input of another decade counter. Because they are dual packages, this will give you two more digit places which if switched into the lower resolution position will take it all the way down to 1Hz. Of course you will need a bigger display of at least 7 digits.
On the decade counter chips themselves. These were carefully selected for upward compatibility and a few other reasons I can't remember off hand. I think the chip you are discussing, the '47 is not an actual decade counter but more of a chaser circuit. It will not work! I have built these with 74hc160 decade counters but have a problem getting them these days so I would stick with the 74hc390's. If you want maximum high speed performance without a prescaler you might look into getting the "AHCT" variety of counter chips. For instance a 74AHCT390. This stands for "Advanced High speed CMOS" and I do know that Texas Instruments makes them.
Meaning, from your 390s can I simply drive my 47s instead of driving your 4543s. The 7447 is a BCD to 7-segment converter.
Thanks for your help with the other big question. I wasn't sure if it was actually counting the signals in a duration and passing the carry over to the next counter. I wrote of not actually increasing the TOP end of the counter, but decimating (decimal pointing) additional characters below 1HZ. Your 5 digit unit does me well (I want it to do <9999.9HZ or <9.9999kHZ). What I don't understand is, if I have a signal at say 2323.5HZ, how can your circuit measure the .5 when you wrote of it counting the higher places first? I looked at your schematic and the input's first counter (from 7408) drives the farthest right digit, ascending from there. This would work, and as the ones carry to the tens, that carry to the hundreds,etc., a total count for a duration would get displayed (updated on a frequent basis so the display doesn't flutter, which is your 4060 & J-K). Right? But in that means it's only counting full pulses, no matter how many times I divide between the the right most characters (J-K and additional dividers), the farthest right character will still always only be a full pulse. Am I missing something here?
As you suggested, in the 100HZ mode, I would then need at least two additional 390s, one to bring it down to 1HZ, and another to bring it down to .01HZ. If I ONLY utilize a 5-digit display, I would need to omit half of one of the 390s and run it's output to my first "whole 390" divider and then to your first 390's input (to read 9999.9HZ). Then those dividers I would be using solely to divide timeline (if that's what they are doing), won't be driving any characters. Right? Is it really counting left to right ??? I just don't see it in your schematic! Please explain...
Meaning, from your 390s can I simply drive my 47s instead of driving your 4543s. The 7447 is a BCD to 7-segment converter.
Thanks for your help with the other big question. I wasn't sure if it was actually counting the signals in a duration and passing the carry over to the next counter. I wrote of not actually increasing the TOP end of the counter, but decimating (decimal pointing) additional characters below 1HZ. Your 5 digit unit does me well (I want it to do <9999.9HZ or <9.9999kHZ). What I don't understand is, if I have a signal at say 2323.5HZ, how can your circuit measure the .5 when you wrote of it counting the higher places first? I looked at your schematic and the input's first counter (from 7408) drives the farthest right digit, ascending from there. This would work, and as the ones carry to the tens, that carry to the hundreds,etc., a total count for a duration would get displayed (updated on a frequent basis so the display doesn't flutter, which is your 4060 & J-K). Right? But in that means it's only counting full pulses, no matter how many times I divide between the the right most characters (J-K and additional dividers), the farthest right character will still always only be a full pulse. Am I missing something here?
As you suggested, in the 100HZ mode, I would then need at least two additional 390s, one to bring it down to 1HZ, and another to bring it down to .01HZ. If I ONLY utilize a 5-digit display, I would need to omit half of one of the 390s and run it's output to my first "whole 390" divider and then to your first 390's input (to read 9999.9HZ). Then those dividers I would be using solely to divide timeline (if that's what they are doing), won't be driving any characters. Right? Is it really counting left to right ??? I just don't see it in your schematic! Please explain...
OK, yes it counts left to right. I do not see a problem using the 7447's. As long as you have a BCD input which is what the '390s will provide then should work fine. Just make sure Qd is connected to the MSB (Most Significant Bit) position.
And yes you can stick with the 5 digit display but you still need to add one more '390 chip to the end of the string (between J-K flip flop) to get to 1HZ and one more half chip for tenths of a Hz. As you stated, there are two counters in each package. As far as shifting all the digits further to the left, you will need to get the "LD" and "BI" and "inverted CLR"signals off the last counter.
That is very nice Boncuk. I hope that goes for anyone. It is a handy bench tool. Personally I like a good rf front end on them so that you can even read a signal off the air. This was just a basic building block of the internals of a counter. You could expand it all sorts of ways to be a deluxe read down to one Hz to just something simple as was posted. Personally I will contact you;
Actually, further investigation of the 4543 you utilize reveals it as a latch/decoder/driver, which means it holds it's last signal until the latch is disabled and the new entry addressed. This means the 7447 won't do. Correct?
By dividing the signal for a more precise decimal reading at lower frequencies, I am actually increasing the gate (sample) duration, so for me to read down to a tenth of a Hz, I will be sampling the signal for 10 seconds, which is how I will get the "partial" pulses. That's what I get with the timer halfing the AND with the signal. I would just have to wait 10 seconds to get a reading between 0000.0 and 9999.9. Correct??
The Motorola spec sheet for the 4543 (14543) notes an LED display could be driven, but the IC only supplies about 10ma per segment. Not much. It suggests it's "Phase" be connected to low for C/C Leds, and high for C/A Leds, but it also suggests for higher draws (VDD <= 10 V or Iout >= 10 mA) that a bipolar transistor be used. Anybody, I'm sure a Darlington driver array (such as a ULN2003a, for 5V devices) would do "the trick", but I don't need 500ma for each segment. How about a package that supplies less current, w/o me having to do 35 transistors individually ?? If I do the Qs individually, which (TO-92) might someone suggest for this common cathode task?
I would NO LONGER be feeding the square wave signal from the 4096 bit connection (Q13 / pin 2) to the Phase on the 4543 (or the Leds common cathode/anode), because all it's for is the needed square wave to the LCD plane and timing of the chips that drive it (rudimentary single-phase alternating current). Correct ??
Actually, further investigation of the 4543 you utilize reveals it as a latch/decoder/driver, which means it holds it's last signal until the latch is disabled and the new entry addressed. This means the 7447 won't do. Correct?
By dividing the signal for a more precise decimal reading at lower frequencies, I am actually increasing the gate (sample) duration, so for me to read down to a tenth of a Hz, I will be sampling the signal for 10 seconds, which is how I will get the "partial" pulses. That's what I get with the timer halfing the AND with the signal. I would just have to wait 10 seconds to get a reading between 0000.0 and 9999.9. Correct??
The Motorola spec sheet for the 4543 (14543) notes an LED display could be driven, but the IC only supplies about 10ma per segment. Not much. It suggests it's "Phase" be connected to low for C/C Leds, and high for C/A Leds, but it also suggests for higher draws (VDD <= 10 V or Iout >= 10 mA) that a bipolar transistor be used. Anybody, I'm sure a Darlington driver array (such as a ULN2003a, for 5V devices) would do "the trick", but I don't need 500ma for each segment. How about a package that supplies less current, w/o me having to do 35 transistors individually ?? If I do the Qs individually, which (TO-92) might someone suggest for this common cathode task?
I would NO LONGER be feeding the square wave signal from the 4096 bit connection (Q13 / pin 2) to the Phase on the 4543 (or the Leds common cathode/anode), because all it's for is the needed square wave to the LCD plane and timing of the chips that drive it (rudimentary single-phase alternating current). Correct ??
Actually I think the 7447 would work. You see, the display drivers can be thought of as a separate entity from the counting process. All they do is take a BCD value and drive the LEDs appropriately.
So for gong to higher resolutions it will be done by adding counters. If you want more digits you simply use the Qd output to feed the next counter. This in effect is taking the remainder from the last decimal place and passing it along to another counter to be broken down into its BCD code.
So try to thin of it as two separate systems. One that does the division (counting) and the other is merely a display. The display portion does not effect the counting process. It is just a dumb and happy 7 segment display that will display what the counters are feeding to it.
I understand what you write, but what I'm saying is, your circuit has a crystal controlled oscillator (32MHz), with the 4060 dividing it by 32 for a clock output of 1KHz. Then (depending on switch position), that clock signal either gets divided by ten or passed as is, onto the AND gate, which enables the incoming measured frequency to pass the pulses (FULL WHOLE pulses) through to the BCDs, throughout the specifed duration of the clock enabled AND. The BCDs count the full whole pulses which are then decoded and displayed.
The first BCD is IC4a (receiving the signal of measurement from the AND), and that BCD drives the ones (farthest right character) on your display. As I further keep dividing the incoming signal, I get more digits, and they are to the left of the "ones" (tens/hundreds/Ks/10Ks). That's what I see in the context of your circuit. If I add additional signal dividers (anywhere), I am simply expanding the total number of characters for counting the measured signal (to 100Ks, 1Ms, etc.), because the incoming signal is having the total full pulse count DIVIDED. But I'm trying to go the other way. If I divide the measured signal before the first BCD, I am also going the wrong way (the ones become tens, etc.). There is no way to measure a tenth of a cycle using a counter triggered by whole pulses, no matter if/where the signal is being divided (because all it's doing then is expanding the maximum count displayed by moving the decimal point to the right, and I want the decimal point to go to the left!).
There is only two ways to measure the decimal part of a cycle. Either use a PWM signal that references / calculates the signal, to figure out how many times it can fit that signal's duration between highs into one second (ex.-a signal with .005 seconds between pulses works out to 200hz.), but that's not what your circuit is doing. Your circuit counts the number of signals in a duration of time which your clock identifies as less than one second (1KHz/100Hz), so it's impossible for your counters to determine a decimal value (if a signal pulse is 100.1Hz, that means once every ten seconds it would count to 101 instead of 100). The only way to measure such an indifference (by counting) would be to sample the signal for a longer duration (in ten seconds it would count up 900 <9*100> plus 101 <the tenth second> for a total of 1001, and with the decimal point between the ones/tens, that count would display as "100.1").
Adding a divider (BCD/Driver) to the signal after your string <IC6A> has no affect because IC6A drives the fifth digit (10Ks). My signal (9999.9 or less) is less than 4 whole digits, and I want to utilize the fifth digit (the farthest right digit, driven by IC4A which gets the signal) as the decimal digit. I can only see doing this by sampling for a duration longer than your clock supplies (.1Hz), which means dividing the 100Hz by 3 more BCDs, thereby allowing the counter to count up to 99,999 in a ten second duration, for a frequency of 9999.9Hz. Make sense?
The 7447 won't work, because everytime the signal is counted, the driver will display the counting progress in the 74LS390s as they change. Your 4543 is a chip I had never seen, which stores the BCD code, decodes and drives the display (identified as a latch/decoder/driver), until it is told to Blank and Latch Disable the current values stored, and then the next present BCD codes get stored as these pins status' change.
Sorry if I seem insistent on the counter (all by itself) not being able to determine decimals, but the counter is counting whole pulses (on the negative edge). Your circuit has a "gate" (sample rate) of 1000 or 100 times per second, enabling the measured frequency to be passed onto the counters (through the AND). Without PWM and calculation, the only way to count up partial signals is to increase the gate so when each second's multiple partial signals add up to more than one full pulse, it will be counted. That would have to be done with a much slower gate than your circuit provides.
Anybody on the Bi-Polar transistor array driver thing, for less than 500ma per channel (segment)? What about a TO-92 which would be ideal w/o extra discreet components? Am I correct about the LCD plane's operation? <re how it works re the needed "square wave" signal, since I'm not into LCD and have never built anything with one>
Yeah your right. The sample pulse has to come down as well. Let me think about it. I was trying to steer you away from the display portion of it. The display is OK. I see no reason the 7447 should not work. So let's figure this out. With a binary divide you will not come up with 1/10th Hz. For the sake of simplicity let's just say 1Hz for now.
I believe it may work the same because the remainder will be displayed. Think about it. I was able to display 100 Hz resolution using 1KHz samples. Just in case it doesn't then what you will need to do is come off the 1KHz output of the '4060 into some decade counters. Just use more '390s. When you get to 1Hz, which means 3 counters or two chips, then you can use the other half of the J-K flip flop to square it off to a 50% duty cycle.
From there there are at least a couple of approaches you can use. The most straight forward would be to use the 1Hz signal after J-K to latch all the counters.
But the 1Hz wont do decimals. Think about it like this. An oval race track, and each time the leading car passes the finish line, the lap count increases. The finish line is the negative going edge that the 390s count. So, if the car makes 10.5 laps in 6 minutes, by only sampling every six minutes, the total count will be 10, the number of times it passed the finish line (the negative going edge for the counters). Then the counter gets reset to 0 to start all over again for the next 6 minutes. It will never, ever count more than 10 laps if the vehicle stays at 10.5 laps every 6 minutes. But in all actuality, the vehicle is moving 10.5 laps every six minutes.
If I count the number of laps for 60 minutes, the vehicle will pass the finish line 105 times. By turning on the first decimal point, I'm displaying the figure as having been divided by ten (to reduce the 60 minute gate back to 6 minutes), and the display will show 10.5, the number of laps the vehicle makes every 6 minutes. Think of the 1Hz as 6 minutes, or any time duration. Even if I set this example as 10.5 laps in a second and it's a fighter jet rolling around the oval, to get the partial laps added up I would need to increase the sample gate. If I wanted to go to the hundreths, using your "count for a duration" circuit, I would need to sample 100 seconds, or I will always reset the counter and not add up the partials. But sampling every 100 seconds is a bit too much and I don't need that much resolution.
Back to the 1Hz thing. If I have a signal of 5500.75 in a second, you know. But I'm losing the .75 everytime the counter resets, every second. I will never get decimals. If I sample it for longer than a second (10, since with it I can readily divide the displayed results by simply lighting up a decimal point), It would count up to 55007 with a 5 digit counter, for a total count of 55007 (55007.5) and it would display as "5500.7" which gives me the tenths (though I would lose the .05*10, which I don't need <beyond the tenths>). If I did need beyond the tenths, I could do what you say and expand the counter's range, but for every added digit to accommodate additional decimal places, I would need to divide the timer by 10 more thereby increasing it's gate sample. It will be hell waiting 10 seconds for a reading, but your circuit is the basis I needed to subdue my 3-1/2 digit DVM, and allow me to 100 fold the monitoring and tuning accuracy of my timer's output (by being able to display the ones <since the signal is larger than 1999> and the tenths).
The most straight forward would be to use the 1Hz signal after J-K to latch all the counters.
Your not latching the counters with the J-K, you're resetting them, but first latching the latch/decoder/driver and enabling the AND to pass the signal being measured. The counters are always counting when the signal is applied, and when the latch/decoder/driver changes state (Latch Disable <LD> and Blank <BL>), it erases it's stored binary code that was previously loaded from the counters and loads the new binary codes / decodes / displays the results. Shortly thereafter this same signal resets the counters (the Q1 circuit in the lower left corner). But I'm also thinking, that I would have to wait ten more seconds to start the next gate, or reset the J-K WHEN/SHORTLY AFTER the 390s have their Master Reset go high (pin 2). Maybe I could somehow do this from that same delay circuit used to reset the 390s...?
The clear (MR) on your divider 390 (IC6B pin 14) is always grounded. Only the counter 390s have their MR states change, through the delay circuit. If I leave your divider as well as all of my 3 additional dividers always grounded, then the J-K will flip/flop every ten seconds, when the divided clock signal changes. I'm wondering if I reset these dividers through the delay circuit, if there will be enough time for the binary codes to load into the latch/decoder/drivers and/or if the flip-flop won't excessively oscillate at a rate equal to the delay timer. Your circuit doesn't reset the divider but it works, but that's also because your flip-flop is cycling 100 or 1000 times a second, so you wouldn't notice if it was blanked for a hundreth of a second and then displayed for a hundreth of a second. With my ten second gate, I would have the display blank for ten seconds, then display the most recent latched/decoded binary values for ten seconds. I want it to display for ten seconds, blank (long enough to load the BCD codes), and then start counting all over again (which would require the J-K to reset, but since it's being used in toggle mode, I would actually have to reset it's clock input back to low, hence, MR the divider 390s). Any idears ??
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