Cheap / Low Power Simple Freq. Counter

[Space Varmint]

I cannot post in "Projects" so I put the schematic over here: https://www.aaroncake.net/forum/topic.asp?TOPIC_ID=8555

A very handy bench tool for you newbies.

 

[audioguru]

I don't see your schematic, just one photo.

 

[Space Varmint]

I put it at the link because I can't post in projects. Just click the link.

 

[Space Varmint]

OK here is a Black & White version. I like to do this when I hand wire stuff with allot of connects to some sort of bus. I will re-size it with printer software so it is all on one page and print it out and tape it to the wall in front of my bench.

 

[audioguru]

My fluke DMM has a pretty good frequency counter so I have never made one.

 

[Space Varmint]

Yeah, those Flukes do it all but they are kinda pricey. How high an input frequency can you read? This thing right here will go as high as you possibly can go without a prescaler. So you can just add one to the front of this. Another thing is when you are reading in the tens of megahertz, if you want it to read higher than 40 to 50MHz which is pretty typical, then you want the fastest chips you can get for the counters the 74hc390s. I'm not sure if they come in AHCT. If they do it would be 74AHCT390. That should get you probably 99MHz top fvrequency without a prescaler.

 

[Mikebits]

What is the deal with using a capacitive coupled CE amp to drive the clear pins on your counters?

 

[Space Varmint]

What is the deal with using a capacitive coupled CE amp to drive the clear pins on your counters?

Very good question Mikey. I wanted to keep the chip count down as low as possible so I made an "Inverter Gate" with a transistor rather than use an 74hc04 and have all those unused gates running. I know I could strap the unused gates high on the inputs but I needed to eliminate the chip so I would have room for the J-K flop flip to square off the output signal of the Qd output of the last decade counter.

 

[Mikebits]

Well, instead of using the 7408 AND gate, you could have used a 7400 NAND gate with 2 NANDS configured to make a AND gate leaving you two inverters. Same chip count.

 

[Space Varmint]

Well, instead of using the 7408 AND gate, you could have used a 7400 NAND gate with 2 NANDS configured to make a AND gate leaving you two inverters. Same chip count.

Another very good point. I should have thought of that.

edit*

Yeah, I could have dropped the transistor stage too. I might go ahead and do that in the schematic.

 

[BrownOut]

Good job! How long did it take to wire up?

 

[Space Varmint]

About 2 days & thanks

 

[Mikebits]

Well, the current transistor config will produce rounded edges and produce erratic results. If you really want to keep the transistor I would do the following:
Delete - C4, R4, R5
Replace C3 with a 4.7k resistor
Change - R6 collector resistor to something like 4.7k (Not mandatory but will increase switching times)

These changes will give a much more reliable transistor logic switch. And reduce parts count in the process

Overall I commend you for putting all that together. Nice job on schematic as well.

 

[Hero999]

I have a frequency counter that works up to 1.3GHz. I can't remember the brand (I'll check if you like) but frequency counters aren't expensive.

 

[Space Varmint]

Well, the current transistor config will produce rounded edges and produce erratic results. If you really want to keep the transistor I would do the following:
Delete - C4, R4, R5
Replace C3 with a 4.7k resistor
Change - R6 collector resistor to something like 4.7k (Not mandatory but will increase switching times)

These changes will give a much more reliable transistor logic switch. And reduce parts count in the process

Overall I commend you for putting all that together. Nice job on schematic as well.

Where did you get that? Some Spice program? First of all the self bias keeps it pretty even throughout and the collector resistance was used to match the high impedance CMOS and it is broadband. Remember we are not concerned with signal integrity but rather how many pulses pass through it's full frequency spectrum. So I am not concerned with rounded edges although there are hardly any noticeable rounded edges. And how do you come up with that since the only capacitance in that part of the circuit is the very minimal transistor junction capacitance. The 1uF cap. is for passing the lower freqs. and by decoupling I decrease the DC load effects making the bias less critical.

 

[BrownOut]

When you get the schematic fanalized, put it in the "circuits" section. Then the next time someone tells me it can't be done without a PIC, I'll just point to this.

 

[Mikebits]

Where did you get that? Some Spice program? First of all the self bias keeps it pretty even throughout and the collector resistance was used to match the high impedance CMOS and it is broadband. Remember we are not concerned with signal integrity but rather how many pulses pass through it's full frequency spectrum. So I am not concerned with rounded edges although there are hardly any noticeable rounded edges. And how do you come up with that since the only capacitance in that part of the circuit is the very minimal transistor junction capacitance. The 1uF cap. is for passing the lower freqs. and by decoupling I decrease the DC load effects making the bias less critical.

No I did not simulate it and did not need to as this is so basic. Firstly I have never seen a coupling cap used in a digital circuit. Your coupling cap along with the emitter resistance makes a differentiator and you will have slow rising edges. And you most certainly do care about signal quality, slow edges can cause false triggering in digital logic sharp edges in digital logic is of utmost importance to minimize double clocking and other false triggers as you approach Vih of the logic. Your emitter resistor is negative feedback and reduces the gain of your switch which lowers your Voh. And the collector to base feedback? I can only imagine what this is doing to your waveform.
You say you verified signal quality, what did you use, a 5MHz Heathkit scope with a 20 inch ground lead on the scope probe? You can take my advice or leave it, I am not going to belabor this into another 40 page thread.

 

[Space Varmint]

No I did not simulate it and did not need to as this is so basic. Firstly I have never seen a coupling cap used in a digital circuit. Your coupling cap along with the emitter resistance makes a differentiator and you will have slow rising edges. And you most certainly do care about signal quality, slow edges can cause false triggering in digital logic sharp edges in digital logic is of utmost importance to minimize double clocking and other false triggers as you approach Vih of the logic. Your emitter resistor is negative feedback and reduces the gain of your switch which lowers your Voh. And the collector to base feedback? I can only imagine what this is doing to your waveform.
You say you verified signal quality, what did you use, a 5MHz Heathkit scope with a 20 inch ground lead on the scope probe? You can take my advice or leave it, I am not going to belabor this into another 40 page thread.

Ha Ha Ha Ha, you are a lark! You need to put a bridal strap on that ego. Gee, does an emitter resistor cause negative feedback? What does that have to do with the price of rice in China? And M-m-m-m-ikey, signal intefrity does not matter when you are counting pulses. You need to do what is best to count pulses. Mikey you have not changed a Mikeybit. Trust me my man. Humilty is the way to greatness. I bet you are afraid to ask questions when you could be learning, because you are afraid someone might think you actually don't know it all. So the best you can do is insult my equipment? Good job Mikey. Next you'll be telling me it's just in the genes. Did I take the time to make the most perfect transistor inverter the world has ever seen? The anwer is "No". Should I?

edit*

Oh, I had to address the differentiator part of your statement.....where?

 

[Boncuk]

Very good question Mikey. I wanted to keep the chip count down as low as possible so I made an "Inverter Gate" with a transistor rather than use an 74hc04 and have all those unused gates running. I know I could strap the unused gates high on the inputs but I needed to eliminate the chip so I would have room for the J-K flop flip to square off the output signal of the Qd output of the last decade counter.

Here is an inverting Schmitt-Trigger with just five pins (74AUP1G14 ,NXP semic). Using a transistor the part count is higher.

 

[Mikebits]

Ha Ha Ha Ha, you are a lark! You need to put a bridal strap on that ego. Gee, does an emitter resistor cause negative feedback? What does that have to do with the price of rice in China? And M-m-m-m-ikey, signal intefrity does not matter when you are counting pulses. You need to do what is best to count pulses. Mikey you have not changed a Mikeybit. Trust me my man. Humilty is the way to greatness. I bet you are afraid to ask questions when you could be learning, because you are afraid someone might think you actually don't know it all. So the best you can do is insult my equipment? Good job Mikey. Next you'll be telling me it's just in the genes. Did I take the time to make the most perfect transistor inverter the world has ever seen? The anwer is "No". Should I?

edit*

Oh, I had to address the differentiator part of your statement.....where?

First of all, I am not 5 yrs old so don't call me Mikey. Don't make me fly to Georgia and bust out your tooth.