Analog Amplifier Design [need assistance for the next couple of hours]

[EEngineer]

Dear all,

We have been assigned a bonus project that upon completion will reward us with an extra 20% on our grade! (yes crazy, but its definitely out of our league)

This is what the assignment handout reads:
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1.1 DESIGN REQUIREMENTS
Design an amplifier with a minimum gain of 10 @ 10 KHz, minimum voltage swing of 5 volts (p-p) at the output, maximum output resistance of 1 kΩ, and minimum input resistance of 50 kΩ. You may use up to 2 transistors (e.g two 2N7000 MOSFETs or two PN2222 BJTs, or one MOSFET and one BJT). Make sure that you only use standard resistors. Use only one power supply with a voltage of 12 volts. Make sure the distortion is minimized (i.e. bias the transistors away from cut-off or triode/saturation). It is ok to have a design better than the specifications (e.g. gain > 10, or Rout < 1 kΩ). Simulate your circuit on Multisim BEFORE the lab session.

1.2 LAB WORK
a) Assemble your design in the lab. Measure and record the DC values of the voltages for all the nodes of your circuit. Estimate the currents.

b) Choose Vsig to be 250*sin(20000π t) mV (i.e. 500 mV p-to-p). Measure the AC output voltage. Plot the input and output signals on the same screen. What is the voltage gain Vo/Vsig? Compare it with your theoretical calculation.

c) Measure the input resistance by measuring the AC voltage of the base/gate and the input voltage Vsig. Compare it with your theoretical calculation.

d) Measure the output resistance by measuring the gain, once for a load resistor of 1 kΩ and once by measuring the gain without the load resistor. Estimate the output resistance based on the two measurements. Compare it with your theoretical calculation.

1.3 RESULTS
1) Measurements:
Measure the DC and AC voltages of all the nodes of the circuit. Measure the voltage gain Vo/Vsig, input resistance, and output resistance and compare them with your theoretical calculations.

2) Simulation:
Simulate your circuit on Multisim. Include the plots of input and output voltages in your report.

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Just finished making a 1L coffee jug. I have been preparing for the past 2 hours on transistors (BJT and MOSFET's) and I still feel that I do not understand circuit examples that are presented. However, the most helpful and simplified reading I got my hands on was the following:

**broken link removed**

Correct me if I'm wrong but I think using 2 BJT's in the Common Emitter configuration would be the way to go on this.

Anyhow, How should I start tackling this problem?

Your input is greatly appreciated.

 

[crutschow]

Two BJT's in a common emitter configuration should work. The requirements are not that difficult.

Generate a design and simulate it. If doesn't meet a requirement then look at the signals at the various nodes, try to determine what might be wrong, and then redesign it. Nothing beats building a design and actually observing how it works.

 

[EEngineer]

Well the thing is the professor will only count the best 3 designs, meaning he doesn't just want a working design but a rather perfect design.

What do you say about building a Common-Emitter gain stage then buffering it with an Emitter-Follower?

 

[crutschow]

Well the thing is the professor will only count the best 3 designs, meaning he doesn't just want a working design but a rather perfect design.

What do you say about building a Common-Emitter gain stage then buffering it with an Emitter-Follower?

That, of course, would give you a lower output impedance, and you should still be able to get a gain of 10 from the first common-emitter stage. But either configuration should work.

 

[kchriste]

Well the thing is the professor will only count the best 3 designs, meaning he doesn't just want a working design but a rather perfect design.

The winning design will not be the best one, but rather the one the instructor likes the best. It helps to know your instructor very well and have paid very close attention in class to succeed at this.

 

[unclejed613]

well, i got it in 10min, ballparked gain of 17. the best device for at least the first stage will be a 2N3904 with an average beta of 200 at 10ma Ic. beyond that i don't want to do your work for you, but i hope this helps get you started.

 

[EEngineer]

Ok, the first equation I used was input resistance,

1. r∏ = (β+1) Re;

I looked up the value of beta for a PN2222 BJT, and sources say its 100.
R∏ = 50kΩ

Therefore, Re = 495Ω.

Now moving the Voltage Gain equation,

2. Vo/Vi = [ β(Rc || Ro) ] / (Rs + r∏).

Ro = 1kΩ (from given requirements)

I am stuck here. I have the value of Re, β and Ro but what about Rc and Rs?

 

[EEngineer]

unclejed613, unfortunately we can not use anything other than a 2N7000 MOSFET or a PN2222 BJT or a combination of both. Up to two transistors may only be used.

But thats a nice gain!

 

[unclejed613]

not bad..... when i simmed it, it came out with a gain of 24. definitely a common emitter with a 2N3904 is a good way to start.

 

[EEngineer]

In our lab, we only have a PN2222 BJT available for use. So I would be able to implement this with a 2N3904.

 

[unclejed613]

2N2222 has a beta of 200, but at a higher Ic.... look at the data sheets for the two devices. one thing you need to look at is the Hfe vs Ic curves.

 

[EEngineer]

ok for β = 200 my modified calculations would be:

1. r∏ = (β+1) Re;

R∏ = 50kΩ

Therefore, Re = 250Ω.

2. Vo/Vi = [ β(Rc || Ro) ] / (Rs + r∏).

Ro = 1kΩ (from given requirements)

I am STILL stuck here. I have the value of Re, β and Ro but what about Rc and Rs?

 

[unclejed613]

Rc, you have to select, and it also has the most effect on the gain. Rs is the output impedance of your signal generator, and i assumed 50 ohms (although it could be as high as 600 ohms for an older signal generator). RE is the emitter resistor, Re is the internal emitter resistance (again, you need to look at data sheet curves to derive this figure). it may also be in the data sheet if it's an extensive one (more than 3 pages). the data sheet i have for the 2N2222 has it listed as 60 ohms.

 

[EEngineer]

Ok, I got totally confused. I am starting everything from scratch again.

The transistor type is PN2222 and not the 2N2222.

Question #1: How do I find the internal emitter resistance from a data sheet?

Question #2: Having found the internal emitter resistance (re), the formula for the input resistance of a Common-Emitter transistor is:

Rin = Rb || (beta + 1) re.

and beta is 100 for a PN2222.

Hence, Rin = Rb || (101) re

Now how on earth would I achieve a minimum input resistance of 50k ohms with the above fomula?

After some thinking, I've looked at the Common-Emitter with Emitter Resistance of which the input resistance formula is:

Rin = Rb || (101) (re + Re),

So I thought maybe I can use a value for Re high enough to achieve the 50k, but then looking at the voltage gain formula, the Re would be hindering it!

Any input?

 

[Hayato]

PN2222 is a replacement for 2N2222 so theres not much difference.

Input resistence is given by the base bias resistors in parallel. Which model are you using Hybrid PI or T?
if Hybrid, the rpi = Vt/IB (base bias current)
if T, re = Vt/IE (emitter bias current)
Where Vt is the thermal voltage ~ 26mV

 

[unclejed613]

use an emitter follower for the input stage, and a common emitter for the output stage. of course, all of your gain will be in the common emitter stage.

 

[audioguru]

I think a "perfect" design will have a performance that is much better than the minimum specs.
Use the 2N7000 Mosfet at the input for an extremely high input resistance and boostrap its input resistor for an even higher input impedance.
It can drive a common-emitter voltage amplifier PN2222 transistor.

 

[unclejed613]

tnx audioguru i forgot he had MOSFETs available. i just put something together with a 2N7000, single stage common source with a gain of 30, input impedance 1Meg, output impedance 1k. the trick is that with a MOSFET, the bias network can be isolated with a 1Meg resistor. i'll let the OP take it from there.....

 

[k7elp60]

I agree with other posters, you need to use the fet as an input as an souce follower for the high imput impedance. As I recall if you design a common emitter amplifer and center bias it, that is to say the collecter at 0 input signal is near 1/2 Vcc you will get a good unclipped sinewave on the output.
The attacted diagram is a typical design for center biasing a common emitter amplifer. In this design the gain is pretty darn close to Rc/Re. Yea is is for a 2n3904 but it can be redone for a different transistor. Also if I remember correctly the Ib biasing resistors affect the input impedance and are essentially in parallel for the AC signal. A further need for the FET as the input amplifier.

 

[unclejed613]

ok, i didn't want to do the OP's work for him, but here's what i came up with. the 2N7002 and the 2N7000 are almost identical with the only real differences being the max Id and Vds. notice the bias network isolated by a 1Meg resistor. this is one of the advantages of using MOSFETs, the bias only needs to be a voltage. play with the bias point and the drain resistor. the source bypass cap gives the stage higher AC gain while allowing the source resistor to provide a stable DC operating point. adjust the source resistor as needed.