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Tank resonance locator

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I thought you knew how the 4046 works... pin 14 is for a low level AC input signal
if you dont understand how to design this, how are you expected to find a solution?

IF you dont have a counter do you know how to calibrate VCO precisely to 1%?

To make the automated circuit you imagine... think of block diagrams then and specify all inputs and outputs.
  1. VCO: 0-Vcc input, 5:1 freq range output, 300R output (internal ) impedance
  2. Low impedance Driver: for 5 Ohm load.
  3. driver to 0.5Ohm parallel resonator with 5 Ohm current sense to ground.
  4. Precision rectifier Op Amp for resonant peak signal. Vp
  5. Negative sweep integrator sample and hold circuit for V_ctrl
  6. 1 shot cct to dump Cap voltage to Vcc with MOSFET switch to restart sweep.
  7. Sample and hold cct #2 for peak signal. (low leakage switch & low leakage Film cap)
  8. Comparator between V(t) - V(t-1) between S&H#2 cap and rectifier out , +Ve out if signal > Hold voltage to resample during pulse .. logic level out.
  9. ! shot timer to stop test if resample pulse has not occurred within 1 ms and hold V_Ctrl
  10. then use control limits or look up table for Vctrl before it drifts. for V vs F
  11. Or use cheap counter circuit with VCO direct to Crystal input pin with small series cap.
Wow. Yeah. I'm thinking about it now. I'll come up with a schematic and discuss with you. Please wait.
 
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Because of your inexperience, this is why I went with a parallel resonant pulse with Low Z driver and high Z , high gain, high speed limiter to drive a "Good" counter in burst frequency measurement mode with a gated pulse to squelch noise, off center and enable only good pulses into the counter.

In the old days, I would have had access to a precision HP counter where I could measure F using time interval and invert to display frequency using 10MHz clock of 1% resolution for 1 sample of 100kHz and 0.1% resolution of 10 ringing pulses for lower Q circuit.

These days with counters running 100MHz and up, it would be even easier, but gating the envelope is critical for avoiding errors into the limiter without DC drift.
 
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What are the ESR's of Coil , Cap? <1mOhm or more?
 
PC1 is a harmonic mixer. (XOR), thus time delay LPF causes cycle skips near resonance which causes errors. WHen used as a PLL it has a narrow capture range % of Fc unlike PC2.

PC2 is a P/F mixer and modulates between 2.5 and 5V for lag and 0 to 2.5V for lead ( or visa versa) so is better to use.

33074 Op Amp draws 0.5uA which into 0.1uF results in a drift of dV/dt=I/C= 0.5V/s and you need to read voltage within 15mV.
 
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PC1 is a harmonic mixer. (XOR), thus time delay LPF causes cycle skips near resonance which causes errors.
PC2 is a P/F mixer and modulates between 2.5 and 5V for lag and 0 to 2.5V for lead ( or visa versa) so is better to use.

33074 Op Amp draws 0.5uA which into 0.1uF results in a drift of dV/dt=I/C= 0.5V/s and you need to read voltage within 15mV.
Okay. I'll use the comparator 2 (PC2). 33074 worked well last time.
Here is another thing, I rang one of the tanks and it was at 150KHz. Here is a video: **broken link removed**
And this one is 18KHz. video: **broken link removed**
Now, I want to hold this peak voltage and send a signal to stop sweeping. I am not able to figure that part out yet.
This tank was a LC parallel circuit, no resistance. Let's say I want to make a circuit for this.
 
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Did you get ESR of Coil and Cap yet?

You can not hold the 0.1 uF Cap with that Op Amp due to input bias current.
WHen you define the time duration the leakage current * C defines the droop rate.
 
Is this wide range of resonant frequencies for a reason?
What the purpose of it? Can you show the devices and setup?

I need the ESR's to know the Q and decay time (ms) for pulse mode in series or sweep rate in parallel. (df/dt)

Don't you have an RLC meter?
 
Did you get ESR of Coil and Cap yet?

You can not hold the 0.1 uF Cap with that Op Amp due to input bias current.
WHen you define the time duration the leakage current * C defines the droop rate.
I am using CSM150/200 , total 10 caps of 5 parallel pair of caps (of 2 caps in series).
L is made by themselves by using coils (air core), so no datasheet or value of L as such.

Now it is already easier with using a scope and a function generator. I want to replace that with a circuit which you just clamp on and it spits out a value. I don't want to use either a scope, rlc meter or a function generator.
 
Test Equipment Design starts with specs like the range of component values and specs. Without this. We can go on forever until you understand why. SO I will opt out until then. Sorry but without specs or a tester like RLC or scope measures of same with a bridge. to generate specs or some sense of purpose to this device, I'm wasting my time.

This is a very low impedance tank circuit (<<1 Ohm) and there are many better ways to do this and cheap ways, if I know the Q. DO you know how to measure Q with your setup? Fc/BW-3dB
 
Tony Stewart
This is what a one of the tank's caps and coil looks like. Their resonant freq calculated using a scope and a function generator is around 18KHz. Now, I tried measuring the resistance using a multi-meter across the tank, it gave me 0.3 ohms.
Assuming equal resistances I'd say 0.6 ohm ESR for both caps and coil, since it is a parallel tank.
The overall cap is 7.02uF. L can be calculated using the formula to be around 11uH.
Does it help?
 

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11uH <>7uF @ 18kHz , Zo=1.25Ohm
If ESR = 0.3 Ohm then Q is only 4.4 and excitation frequency can be within 25%
but conduction loss is 0.3/1.25= 24% so induction heater efficiency is only 76% max.


This rules out pulse ring test. so I see why you want to sweep it.

ALthough from viewing the coils, it's hard to image almost 1cm thick coils and cables are more than a few mOhms... hmm

I am not sure why you want to limit power in the drive circuit, yet are willing to drive a high current LED display counter circuit.

Using 2 transistors in parallel resonance, you can use rectified feedback to pump the resonator from a 3.7V LiPo for ~ 50mW while on and with. logic level out to a counter display and perform quickly.
 
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Tony Stewart
The reason to limit power is to make the frequency testing circuit small and mobile. If the final circuit will be high power and bulky, it would not be preferred over the "scope and function generator method". This would still require a frequency counter, right? If yes then nobody would want to prefer it over the other method.
 
Is cost and qty significant here? HOw many? what's it worth?

What about using an Arduino?

The best solution comes from detailed requirements.
 
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Is cost and qty significant here? HOw many? what's it worth?

What about using an Arduino?

The best solution comes from detailed requirements.

I just want to build one right now. Its more of a personal thing so that someone who doesn't know how to use a scope and a function generator could use it by just putting across a tank and note the value.

I do not have knowledge of Audrino, never took a course related and is beyond my scope. The best programming I have done is with a TI Picollo mircocontroller. However, I would prefer everything to be mostly analog (using ICs), no matter how big my circuit gets. Keep the cost under $50 for now (final circuit must be independent and must not use a scope, function generator or a freq counter) . Troubleshooting with this problem, I am looking it more as a learning experience than actually making anything to sell.

Now I was looking at the CD4046.
I used two frequency generators and plugged one to pin 14 and other to 3 and tried to understand phase 2 comparator (pin 13, since I had used phase 1 comparator only in the past). When I change frequency through pin 14 (sq wave), output through 13 changes the same way. So, If 14 is a current feedback, output 13 would be aligned as frequency of feedback will change. Will it sweep through the range that I define? How can I hold the value of max. current and signal that this is the resonant freq?
I am planning to use 120V AC input now, convert it to DC and then AC again (sweeping frequency).

Does it seem doable?
 
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Now I was looking at the CD4046.
I used two frequency generators and plugged one to pin 14 and other to 3 and tried to understand phase 2 comparator (pin 13, since I had used phase 1 comparator only in the past). When I change frequency through pin 14 (sq wave), output through 13 changes the same way. So, If 14 is a current feedback, output 13 would be aligned as frequency of feedback will change. Will it sweep through the range that I define? How can I hold the value of max. current and signal that this is the resonant freq?
I am planning to use 120V AC input now, convert it to DC and then AC again (sweeping frequency).

Does it seem doable?
not low power.

Read how PC2 works. It is a tri-state pump up down phase/freq detector so a small cap C is needed or RC/C lag;/lead filter. to charge up. Adjust impedance to control PLL capture time, jitter, PC2 out sag voltage. between pulses....

upload_2015-9-23_19-30-34.png



You don't need high voltage, but you do need reasonably high current (100mA) to energize the tank circuit at 0.5 Ω more or less. Thus using a complementary MOSFET to drive the Tank circuit for maximum voltage at 0.5 Ohm max and rolls off below this away from center. Thus your driver can apply low voltage even as low as 1V but needs to be much lower impedance than 0.5 e.g. 10mΩ Nch/Pch with logic level Gate voltage may work as long as you don't have shoot thru (Vcc short) during transitions by care selection of MOSFETS using 5V drive level.

PLL Signal input should be your tank signal going into a precision limiter with with maybe <1% positive feedback for hysteresis and high gain but logic level out.
No input signal causes PC2 to go to 0V or minimum frequency after VCO filter. Note the PC2 load circuit for PC2 to modulate as I indicated before. Vcc/2 to Vcc for phase lead and 0 to Vcc/2 for phase lag.
When both rising edges are in sync for Sig and Ref ( from VCO, PC2 is in tristate mode.

Thus you can possibly sweep the VCO and if done right should lock onto resonant frequency where phase shift is 0 deg for a parallel tank circuit. and lead /lag otherwise.

Make sense yet?

The limiter from your tank output is critical as is your PC2 output filter and VCO setup. 5V should be adequate for PLL , preferably 3.7 from a LiPo. battery to reach 150kHz.

You need a good driver for the VCO to the tank and you might consider complementary darlington emitter followers from 3.7V to drive 0.5mA in and get maybe 100~ 500mA out which will be 0.25V maybe at resonance, which into a good limiter with 1mV resolution should resolve the small signal to drive the PLL input if you AC couple to minimize input offsets.

If you get it to lock on, then you have succeeded in the hard part.
The easy part is a counter display to count VCO output pulses in 10ms 50kHz = 500 pulses or 2% resolution using BCD counters and BCD decoders to 7 seg display. or 4 digits using 100ms count gate. 150kHz * 100ms = 15000 count needs 5 digits but you can use decimal point for over flow.(1)
 
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not low power.

Read how PC2 works. It is a tri-state pump up down phase/freq detector so a small cap C is needed or RC/C lag;/lead filter. to charge up. Adjust impedance to control PLL capture time, jitter, PC2 out sag voltage. between pulses....

View attachment 94329


You don't need high voltage, but you do need reasonably high current (100mA) to energize the tank circuit at 0.5 Ω more or less. Thus using a complementary MOSFET to drive the Tank circuit for maximum voltage at 0.5 Ohm max and rolls off below this away from center. Thus your driver can apply low voltage even as low as 1V but needs to be much lower impedance than 0.5 e.g. 10mΩ Nch/Pch with logic level Gate voltage may work as long as you don't have shoot thru (Vcc short) during transitions by care selection of MOSFETS using 5V drive level.

PLL Signal input should be your tank signal going into a precision limiter with with maybe <1% positive feedback for hysteresis and high gain but logic level out.
No input signal causes PC2 to go to 0V or minimum frequency after VCO filter. Note the PC2 load circuit for PC2 to modulate as I indicated before. Vcc/2 to Vcc for phase lead and 0 to Vcc/2 for phase lag.
When both rising edges are in sync for Sig and Ref ( from VCO, PC2 is in tristate mode.

Thus you can possibly sweep the VCO and if done right should lock onto resonant frequency where phase shift is 0 deg for a parallel tank circuit. and lead /lag otherwise.

Make sense yet?

The limiter from your tank output is critical as is your PC2 output filter and VCO setup. 5V should be adequate for PLL , preferably 3.7 from a LiPo. battery to reach 150kHz.

You need a good driver for the VCO to the tank and you might consider complementary darlington emitter followers from 3.7V to drive 0.5mA in and get maybe 100~ 500mA out which will be 0.25V maybe at resonance, which into a good limiter with 1mV resolution should resolve the small signal to drive the PLL input if you AC couple to minimize input offsets.

If you get it to lock on, then you have succeeded in the hard part.
The easy part is a counter display to count VCO output pulses in 10ms 50kHz = 500 pulses or 2% resolution using BCD counters and BCD decoders to 7 seg display. or 4 digits using 100ms count gate. 150kHz * 100ms = 15000 count needs 5 digits but you can use decimal point for over flow.(1)
I was thinking along the same lines. I don't if you made it clear that the Comparator input to the phase detector II should be the tank voltage, limited to CMOS levels, and the Signal input to phase comparator II should be the current sense line, amplified and limited to CMOS levels (using a comparator). I don't think any sort of sweep is needed. The loop should settle on the resonant frequency, provided the Q is sufficient, and there is no phase inversion of voltage relative to current in the limiters.

Here's a block diagram.
You still need a frequency counter. You can build or buy one fairly inexpensively.
Resonant freq detector.PNG
 
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I was thinking along the same lines. I don't if you made it clear that the Comparator input to the phase detector II should be the tank voltage, limited to CMOS levels, and the Signal input to phase comparator II should be the current sense line, amplified and limited to CMOS levels (using a comparator). I don't think any sort of sweep is needed. The loop should settle on the resonant frequency, provided the Q is sufficient, and there is no phase inversion of voltage relative to current in the limiters.

Here's a block diagram.
You still need a frequency counter. You can build or buy one fairly inexpensively.
View attachment 94342
not low power.

Read how PC2 works. It is a tri-state pump up down phase/freq detector so a small cap C is needed or RC/C lag;/lead filter. to charge up. Adjust impedance to control PLL capture time, jitter, PC2 out sag voltage. between pulses....

View attachment 94329


You don't need high voltage, but you do need reasonably high current (100mA) to energize the tank circuit at 0.5 Ω more or less. Thus using a complementary MOSFET to drive the Tank circuit for maximum voltage at 0.5 Ohm max and rolls off below this away from center. Thus your driver can apply low voltage even as low as 1V but needs to be much lower impedance than 0.5 e.g. 10mΩ Nch/Pch with logic level Gate voltage may work as long as you don't have shoot thru (Vcc short) during transitions by care selection of MOSFETS using 5V drive level.

PLL Signal input should be your tank signal going into a precision limiter with with maybe <1% positive feedback for hysteresis and high gain but logic level out.
No input signal causes PC2 to go to 0V or minimum frequency after VCO filter. Note the PC2 load circuit for PC2 to modulate as I indicated before. Vcc/2 to Vcc for phase lead and 0 to Vcc/2 for phase lag.
When both rising edges are in sync for Sig and Ref ( from VCO, PC2 is in tristate mode.

Thus you can possibly sweep the VCO and if done right should lock onto resonant frequency where phase shift is 0 deg for a parallel tank circuit. and lead /lag otherwise.

Make sense yet?

The limiter from your tank output is critical as is your PC2 output filter and VCO setup. 5V should be adequate for PLL , preferably 3.7 from a LiPo. battery to reach 150kHz.

You need a good driver for the VCO to the tank and you might consider complementary darlington emitter followers from 3.7V to drive 0.5mA in and get maybe 100~ 500mA out which will be 0.25V maybe at resonance, which into a good limiter with 1mV resolution should resolve the small signal to drive the PLL input if you AC couple to minimize input offsets.

If you get it to lock on, then you have succeeded in the hard part.
The easy part is a counter display to count VCO output pulses in 10ms 50kHz = 500 pulses or 2% resolution using BCD counters and BCD decoders to 7 seg display. or 4 digits using 100ms count gate. 150kHz * 100ms = 15000 count needs 5 digits but you can use decimal point for over flow.(1)
Thank you Tony Stewart and Roff for a detailed suggestion. I had decided to go with a current feedback too. Now the tank is fed through a 120Vac, which goes through a rectifier and then an inverter (so the power is going is going to be higher now). The output of the CD4046 would fire the IGBTs. I have built the power supply for now. I am working on the gate circuits to fire the IGBT modules.
The attachment shows the schematic. Do you think I am in the right direction.

Roff , Could you please guide me how to build a inexpensive freq counter.
 

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To lock onto frequency, the Driver & current sense should be as low or lower than R1 above in ROFF's block diagram.
It is (important to) analyze the control system to define the loop stability gain constants for each stage to understand the challenges of non-linear loop gain with frequency, because sense current changes with frequency unless amplified with non-linear phase on harmonics. Thus a Sine source or a tracking BPF works better.

VCO = ΔV/ΔF

Phase shift in the tank circuit is Δθ/Δt which is almost +/-90 deg over the resonance approx, which means loop gain changes widely over the 10:1 or even50:1 frequency range.

The real problem with this method is that when not at resonance with a sine current, below it is a differentiated square wave from L and above it is an attenuated Triangle wave (integrated Square wave from C) and not a swept sinusoidal signal. Thus the Signal to Noise ratio varies widely and phase response is nonlinear affecting loop gain and stability as well as causing harmonic challenges to the phase detector.

After looking at your schematic again, I see you have spent a good deal of complexity to create VCO symmetry using parasitic properties of RC to create the smallest possible edge trigger pulse using D FF's differential delays into a Schmitt trigger to recover a square wave again.

I am now thinking it is better to integrate a voltage controlled triangle generator, which by definition integrates the odd harmonics 12 dB for every odd harmonic ( 2 octaves) thus improving the current signal off center frequency.

I think the IGBT approach is fine , but neither portable nor low power, both which are still possible.
So have you changed your requirements?

To design a counter, you must specify the accuracy and frequency range. 3k~150kHz +/- 1%? or?? that means a 5 digit display. from 3.00 kHz to 150kHz even though you don't need it for 150k and auto ranging is a requirement you must specify or floating decimal point, which adds complexity to simple CMOS designs.

All these design issues come from not fleshing out the implications of a requirement writing yourself a simple design spec for the system. with impedance range, Q range, accuracy, digital counter display , resolution and accuracy.
 
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