Continue to Site

Welcome to our site!

Electro Tech is an online community (with over 170,000 members) who enjoy talking about and building electronic circuits, projects and gadgets. To participate you need to register. Registration is free. Click here to register now.

  • Welcome to our site! Electro Tech is an online community (with over 170,000 members) who enjoy talking about and building electronic circuits, projects and gadgets. To participate you need to register. Registration is free. Click here to register now.

What techniques to reduce EMI noise from a SMPS?

Status
Not open for further replies.
Simulation schematic for open loop analysis:

**broken link removed**

Opamp is ideal (100dB open loop gain), the voltage controlled voltage source is to model the modulator gain.

Here is the simulation results:

**broken link removed**

The big graph is gain/freq (db/hertz) and the small graph is phase vs frequency (degrees/hertz).
 
Exactly Carl's and my suspicion.
The E/A is going wall to wall.
Unlikely (though not impossible) that it is the loop comp. Improper loop comp waveform is more like a distorted sinewave.

Did you check the wall wart's output waveform?
 
I agree it's unstable, I switched out some components last night and got clean waveforms (no break in pulses) at the switch output but could not get it stable for both light loads and heavy loads. For example I removed C1 and replace C2 with 20pF and could get it stable for about 100 ohm load but heavier loads were unstable.

I actually removed the components and ran open loop and it was stable for very light loads.

Also, about the EA output, isn't the output suppose to go rail to rail? Also, what are the debug steps from here?
 
"Also, about the EA output, isn't the output suppose to go rail to rail?"
The short answer is no. See the last two lines

error-amplifier section TL1451AC
PARAMETER TEST CONDITIONS UNIT MIN TYP† MAX

Positive output voltage swing Vref–0.1 V
Negative output voltage swing 1 V
 
Your error amplifier output should be a DC level (with possible a small amount of 200kHz ripple). Its purpose is to provide a DC voltage that determines the PWM duty-cycle. For steady operation the duty-cycle is constant and so is the error voltage.

I did a quick simulation of your loop and it appears that the phase-shift is 0 degrees where the open loop gain is at least +30dB (normally you want to gain to be no more than -6dB at that point). With that much open loop gain at 0 degrees shift you are pretty much guaranteed a system that will oscillate.

You need to adjust the compensation so that the gain margin is at least -6dB and the phase margin (where the open loop gain goes to 0dB) is at least 45 degrees. Here is a good article on designing stable control loops View attachment Designing Stable .pdf.
 
I did a quick simulation of your loop and it appears that the phase-shift is 0 degrees where the open loop gain is at least +30dB (normally you want to gain to be no more than -6dB at that point). With that much open loop gain at 0 degrees shift you are pretty much guaranteed a system that will oscillate.

How are you doing this simulation? I am not getting the same results.
 
I discovered the discrepancy between our plots. I initially did not put in the 0.5Ω ESR value for C3. With that in, my plots are similar to yours. But without that value of ESR, the plot shows the instability. The problem probably is that you are depending upon the 0.5Ω for stability (which is likely a worst-case value), but your actual capacitor is less then this. If you put a few tenths of an ohm in series with C3 then your converter should become stable.

ESR does significantly improve the phase margin, but it's not good practice to depend upon the ESR of a capacitor for your stability, since only the worst-case maximum value is guaranteed. Better to design the compensation network with the worst-case condition of an ESR=0. That way it will be stable with any value of ESR.

Incidentally, you'll get better plot resolution if you go from about 1Hz to 1MHz. There's no reason to simulate above 10GHz for this system.
 
Issue looks like it's solved.

There were two issues.

One, the feedback values, two, I accidently put the compensation between the positive input and the EA output instead of the negative input and EA output.

After fixing these issues and using C1=20pF,C2=10nF, and R2=100k, I get a very stable output, and the AC noise is suprisingly low (< 20mV). Also I don't get any audible noise no matter what load I have.
 
Status
Not open for further replies.

Latest threads

New Articles From Microcontroller Tips

Back
Top